Abstract A pulse signal having a constant period shorter than that of a quick feed signal and signals transmitted through the actuation of a quick feed switch are used to trigger flipflops and the flipflops deliver signals corresponding to the time of actuation of the switch. The quick feeding operation is performed by applying the quick feed signal to counter circuits only while the signals corresponding to the time of switch actuation are being delivered. In this way, an erroneous operation due to the chattering of the switch can be completely eliminated so that the desired quick feed operation can be accurately performed and that the reference clock signal together with the quick feed signal can be applied to the counter circuits.
Inventors
👤 M Esaki
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-30 20:56
CPC Classifications
G; G04; G04G; G04G5/00; G04G5/02
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
180 words
An electronic digital clock comprising a clock signal generator, a plurality of frequency dividers for dividing the output of said clock signal generator, said frequency dividers providing a quick feed signal at a quick feed output and a control signal at a control output thereof, time display means, and time feeding means for coupling another output of said frequency dividers to said time display means, said time feeding means including time setting means comprising a manual switching means for initiating time feeding, a set signal generator connected to said control output, a set-reset flip-flop circuit having an output terminal and a pair of input terminals, one of which is connected to said manual switching means and the other of which is connected to said set signal generator, a NAND circuit having two input terminals, one of which is connected to said output terminal of said set-reset flip-flop circuit and the other of which is connected to said frequency divider for receiving said quick feed signal, said NAND circuit further including an output terminal operatively connected to said time display means.
Claim 2
Dependent Claim
180 words
An electronic digital clock comprising a clock signal generator, a plurality of frequency dividers for dividing the output of said clock signal generator, said frequency dividers providing a quick feed signal at a quick feed output and a control signal at a control output thereof, time display means, and time feeding means for coupling another output of said frequency dividers to said time display means, said time feeding means including time setting means comprising a manual switching means for initiating time feeding, a set signal generator connected to said control output, a set-reset flip-flop circuit having an output terminal and a pair of input terminals, one of which is connected to said manual switching means and the other of which is connected to said set signal generator, a NAND circuit having two input terminals, one of which is connected to said output terminal of said set-reset flip-flop circuit and the other of which is connected to said frequency divider for receiving said quick feed signal, said NAND circuit further including an output terminal operatively connected to said time display means.
Claim 3
Dependent Claim
54 words
An electronic digital clock according to claim 1 wherein said time feeding means further includes an exclusive OR circuit connected between said NAND circuit and said time display means for taking the exclusive logical sum of the output of said NAND circuit and the divided clock signal from the output of said fequency dividers.