Abstract A burst phase shift keyed receiver which detects, synchronizes and demodulates a phase shift key signal which has an additional 180* phase shift in the center of each transmitted bit. A twostage sample and hold register is fed by the front end of the receiver and triggered at twice the bit rate, the output of each stage, in opposition to each other, are added, thereshold compared, gated with a delayed bit rate synchronizing signal and fed to a shift register that is enabled by a Barker code. The delayed bit synchronizing pulses are achieved by forming two sums of the outputs of the two stages of the sample and hold register, one sum being both the positive outputs and the other sum being the outputs of opposite phase. The two sums are full wave rectified and fed to a comparing threshold circuit, the output thereof feeding a pair of AND gates which are also fed by opposite phases of a divide-by-two flip-flop that is triggered by a delayed 2 times the bit rate signal. The AND gates trigger up or down a counter whose output is threshold detected and fed to a switch together with opposite phases of the flip-flop. The Barker code synchronizing signal is achieved by feeding the output of the front end to a threshold circuit, then to a serial inparallel out shift register, adding the parallel outputs, full wave rectifying, and threshold detecting the sums.
A burst phase shift key receiver for receiving a message derived from a transmitted signal having a carrier and having 180* phase shift in the middle of each transmitted bit comprising: a. means for generating a signal synchronized with the carrier of the transmitted signal; b. an envelope filter fed by the means for generating a synchronized signal; c. an integrator fed by the envelope filter; d. means for generating pulse signals having a frequency of twice the bit rate of the transmitted signal; e. a sample-and-hold register including first and second sample and hold circuits serially interconnected, the sample-and-hold reGister being fed by the integrator and pulsed by the twice the bit rate generating means; f. a first adder fed by the first and second sample-and-hold circuits; g. a first threshold circuit fed by the first adder; h. means for generating bit synchronization pulses fed by said means for generating pulse signals having a frequency of twice the bit rate of the transmitted message; i. a gate fed by the threshold circuit and enabled by the means for generating bit synchronization pulses; j. means for generating Barker code synchronization pulses fed by the integrator; and k. a buffer register fed by the gate circuit and enabled by the Barker code generating means, the output of the buffer register being the received message.
Claim 2
Dependent Claim
223 words
A burst phase shift key receiver for receiving a message derived from a transmitted signal having a carrier and having 180* phase shift in the middle of each transmitted bit comprising: a. means for generating a signal synchronized with the carrier of the transmitted signal; b. an envelope filter fed by the means for generating a synchronized signal; c. an integrator fed by the envelope filter; d. means for generating pulse signals having a frequency of twice the bit rate of the transmitted signal; e. a sample-and-hold register including first and second sample and hold circuits serially interconnected, the sample-and-hold reGister being fed by the integrator and pulsed by the twice the bit rate generating means; f. a first adder fed by the first and second sample-and-hold circuits; g. a first threshold circuit fed by the first adder; h. means for generating bit synchronization pulses fed by said means for generating pulse signals having a frequency of twice the bit rate of the transmitted message; i. a gate fed by the threshold circuit and enabled by the means for generating bit synchronization pulses; j. means for generating Barker code synchronization pulses fed by the integrator; and k. a buffer register fed by the gate circuit and enabled by the Barker code generating means, the output of the buffer register being the received message.
Claim 3
Dependent Claim
158 words
A burst phase shift key receiver according to claim 1 wherein the means for generating bit synchronization pulses comprises in addition to the said first and second sample-and-hold circuits and the first adder: a. a second adder fed by the first and second sample-and-hold circuits; b. a pair of full wave rectifiers fed by one each of the first and second adders; c. a comparing circuit fed by the pair of full wave rectifiers; d. a pair of AND gates fed by the comparing circuit; e. a divide-by-two flip-flop fed by the twice the bit rate generating means and having a pair of outputs in opposite phase enabling one each of the pair of AND gates; f. an up-down counter fed alternatively by the pair of AND gates; g. a threshold comparator circuit fed by the up-down counter; and h. a switch fed by the threshold comparator and activated by the pair of outputs from the divide-by-two flip-flop.
Claim 4
Dependent Claim
92 words
A burst phase shift key receiver according to claim 2 wherein the Barker code synchronizing means comprises: a. a third threshold circuit fed by said integrator; b. a shift register fed by the third threshold circuit and fed by the twice the bit rate generating means and having a plurality of positive and negative parallel otuputs; c. means for adding positive outputs and adding negative outputs of the shift register; d. a full wave rectifier fed by the adding means; and e. a fourth threshold circuit fed by the full wave rectifier.