US3814913A
Expired / Lapsed
US
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Process control apparatus
Assignee: Lucas Electrical Co Ltd
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Filing: 1972-12-13
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Granted: 1974-06-04
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Expires: 1992-12-13
Abstract
Abstract ''''PROCESS CONTROL APPARATUS'''' includes two transducers for measuring two parameters of the process, and a memory unit to which the outputs from the transducers are fed. The memory unit produces an output dependent on the values of the two parameters, this output being binary, and being coupled to a counter which also receives clock pulses. The counter samples the memory unit output, and produces an output pulse when the clock pulse reading is equal to the sample reading. The output pulses are then used to control the process.
Inventors
- 👤 J Ironside
- 👤 D Hodgson
- 👤 M Bertioli
- 👤 M Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:18
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/24; F02D41/2406; G; G05; G05B; G05B11/00; G05B11/01; G05B11/26; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F7/00; G06F7/60; G06F7/62; G06J; G06J1/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
196 words
Process control apparatus in which the process is controlled by an input pulse the duration of which governs the progress of the process, and is to be determined by the values of at least two parameters associated with the process, comprising in combination first and second transducers for measuring the two parameters, a memory unit to which the outputs from the transducers are fed, the memory unit producing a binary output dependent on the values of the two parameters, a counter connected to a source of clock pulses, means whereby the counter samples the memory unit output, then produces an output pulse when a number of clock pulses have been received equal to the sample reading obtained from the memory unit, each output pulse causing the counter to re-sample the memory unit output after which the cycle re-commences, so that the counter produces a succession of output pulses, the time between any two successive output pulses being dependent on the last memory unit output sampled by the counter, means for initiating each input pulse required by the process, and means controlled by the Output pulses from the counter for terminating each input pulse to the process.
Claim 2
Dependent Claim
196 words
Process control apparatus in which the process is controlled by an input pulse the duration of which governs the progress of the process, and is to be determined by the values of at least two parameters associated with the process, comprising in combination first and second transducers for measuring the two parameters, a memory unit to which the outputs from the transducers are fed, the memory unit producing a binary output dependent on the values of the two parameters, a counter connected to a source of clock pulses, means whereby the counter samples the memory unit output, then produces an output pulse when a number of clock pulses have been received equal to the sample reading obtained from the memory unit, each output pulse causing the counter to re-sample the memory unit output after which the cycle re-commences, so that the counter produces a succession of output pulses, the time between any two successive output pulses being dependent on the last memory unit output sampled by the counter, means for initiating each input pulse required by the process, and means controlled by the Output pulses from the counter for terminating each input pulse to the process.
Claim 3
Dependent Claim
26 words
Apparatus as claimed in claim 1 including means responsive to a third process parameter for modifying the time between successive clock pulses fed to the counter.
Claim 4
Dependent Claim
24 words
Apparatus as claimed in claim 2 in which the frequency of the clock pulses is proportional to the value of the third process parameter.
Claim 5
Dependent Claim
31 words
Apparatus as claimed in claim 2 in which there are trains of clock pulses with a delay between trains, the delay being dependent on the value of the third process parameter.
Claim 6
Dependent Claim
28 words
Apparatus as claimed in claim 1 including a logic network sensitive to parameters of the process for preventing production of input pulses to the process in certain circumstances.
Claim 7
Dependent Claim
26 words
Apparatus as claimed in claim 5 in which the logic network always permits an input pulse to the process to be completed once it has started.
Claim 8
Dependent Claim
55 words
Apparatus as claimed in claim 1 in which the means for initiating each input pulse required by the process includes a pulse source producing a control pulse when an input pulse is required, and logic means whereby following a control pulse, the next output pulse from the counter initiates the input pulse to the process.
Claim 9
Dependent Claim
31 words
Apparatus as claimed in claim 7 in which the input pulse to the process is terminated upon production of the nth pulse from the counter, where n is greater than 2.
Claim 10
Dependent Claim
54 words
Apparatus as claimed in claim 8 in which the transducers produce binary signals and each time the counter produces an output, the binary signals have combined therewith different incremental signals to improve the accuracy with which the apparatus computes the required length of the process input pulse for given values of the two parameters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-03 | 1977-12-03 | 1978-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-03 | 1981-12-03 | 1982-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-03 | 1985-12-03 | 1986-06-04 | $7700.00 | Window Closed / Lapsed |