Read-head for an optical character-recognition system

Claim 2

Read head for an optical character-recognition system, the characters being arranged on a line passing in front of said head, including a strip of n photodetectors divided into n'' groups which are essentially in line and approximately perpendicular to the direction of the passing and a switch synchronized by a clock-signal generator coupling sequentially each of the groups of photodetectors with the output of the head, characterized in that the n'' groups are associated with n'' distinct shift registers, respectively, providing the switching, said shift registers being interconnected by a logical closedloop circuit controlling the initiation of sequencing of each group of photodetectors.

Claim 3

Read head according to claim 1, characterized by the photodetectors consisting of photodiodes, the subsystem of diodes of an even-row being coupled to a first shift register, the subsystem of diodes of an odd-row being coupled to a second register.

Claim 4

Read head according to claim 1, characterized by the k-l first stages of a register containing k stages being coupled with k-l inputs of an OR gate whose output is coupled to said closed-loop circuit.

Claim 5

Read head according to claim 1, characterized in that it comprises an output on the last stage of each of the shift registers, an output on each of the OR gates and an input for each of the two shift registers, the logical closed-loop circuit coupling said outputs and said inputs, the registers including, furthermore, at least one input for the clock signals and the strip, two outputs for the read signals.

Claim 6

Read head according to claim 1, characterized by the photodiodes, the shift registers, the OR gates, and their connections being integrated into a microcircuit.

Claim 7

In a read head for an optical character-recognition system, wherein character groups are arranged substantially perpendicular to a direction of motion of said character groups, the combination comprising: a plurality of photodetectors arranged substantially perpendicularly to said direction of motion, said plurality of photodetectors being arranged into n'' photodetector groups; n'' shift registers, each of said shift registers coupled to a one of said photodetector groups, wherein shift register elements of said each shift register are coupled sequentially to photodetectors of said one photodetector groups, said Shift registers being coupled to an output terminal of said read head, said shift registers being activated in response clock signals, wherein said shift register elements receive binary logic data input signals from said coupled photodetectors in response to a read signal; n'' logic NOR gates, each of said NOR gates coupled to a one of said shift registers, wherein an input terminal of a logic NOR gate is connected to all but a final one of shift register elements of said coupled shift register; and circuit means coupled to said shift registers and to said logic NOR circuits for suppressing noise binary logic data contained in said shift register.

Claim 8

In a read head for an optical character-recognition system, wherein character groups are arranged substantially perpendicular to a direction of motion of said character groups, the combination comprising: a plurality of photodetectors arranged substantially perpendicularly to said direction of motion, said plurality of photodetectors being arranged into n'' photodetector groups; n'' shift registers, each of said shift registers coupled to a one of said photodetector groups, wherein shift register elements of said each shift register are coupled sequentially to photodetectors of said one photodetector groups, said Shift registers being coupled to an output terminal of said read head, said shift registers being activated in response clock signals, wherein said shift register elements receive binary logic data input signals from said coupled photodetectors in response to a read signal; n'' logic NOR gates, each of said NOR gates coupled to a one of said shift registers, wherein an input terminal of a logic NOR gate is connected to all but a final one of shift register elements of said coupled shift register; and circuit means coupled to said shift registers and to said logic NOR circuits for suppressing noise binary logic data contained in said shift register.

Claim 9

The combination of claim 6 wherein n'' is equal to 2.

Claim 10

A read head for an optical character-recognition system, said read heading containing a read signal terminal, at least one clock signal terminal, an output terminal and a plurality of terminals for coupling said read head to circuit means, the combination comprising: a plurality of photodetectors coupled to said read signal terminal, said plurality of photodetectors being divided into n'' photodetector groups; n'' shift registers, each shift register coupled to a one of said photodetector groups, photodetector elements of said one photodetector group coupled sequentially to shift register elements of said each shift register, said photodetector elements applying a binary logic data signal to said coupled shift register element in response to a control signal applied to said read signal terminal, each of said shift registers coupled to a clock signal terminal, wherein said shift register is activated by a clock signal applied to said coupled clock signal terminal, said shift registers being coupled to said output terminal, wherein each of said shift registers is coupled to a one said circuit means terminals; and n'' logic NOR gates, wherein each of said NOR gates is said shift registers, wherein a last element of said one shift register is not coupled to said each NOR gate, wherein all remaining shift registers elements of said one shift register are coupled to input terminals of said each NOR gate, wherein output terminals of said NOR gates are coupled to circuit means terminals.

Claim 11

A read head for an optical character-recognition system, said read heading containing a read signal terminal, at least one clock signal terminal, an output terminal and a plurality of terminals for coupling said read head to circuit means, the combination comprising: a plurality of photodetectors coupled to said read signal terminal, said plurality of photodetectors being divided into n'' photodetector groups; n'' shift registers, each shift register coupled to a one of said photodetector groups, photodetector elements of said one photodetector group coupled sequentially to shift register elements of said each shift register, said photodetector elements applying a binary logic data signal to said coupled shift register element in response to a control signal applied to said read signal terminal, each of said shift registers coupled to a clock signal terminal, wherein said shift register is activated by a clock signal applied to said coupled clock signal terminal, said shift registers being coupled to said output terminal, wherein each of said shift registers is coupled to a one said circuit means terminals; and n'' logic NOR gates, wherein each of said NOR gates is said shift registers, wherein a last element of said one shift register is not coupled to said each NOR gate, wherein all remaining shift registers elements of said one shift register are coupled to input terminals of said each NOR gate, wherein output terminals of said NOR gates are coupled to circuit means terminals.

Claim 12

The combination of claim 8 wherein said combination is fabricated into a microcircuit.

Claim 13

The combination of claim 9 wherein n'' is equal to 2.

Claim 14

The combination of claim 10 wherein a first NOR gate is coupled to a first shift register and a second NOR gate is coupled to a second shift register, said circuit means providing a coupling of said first NOR gate to said second shift register and a coupling of said second NOR gate to said first shift register.

Claim 15

In a character-recognition system, the combination of: a plurality of photodetectors arranged in a column simultaneously to receive light signals corresponding to an information column of the character-recognition system, said photodetectors presenting a plurality m of output terminals at which binary signals appear dependent upon the presence and absence of character information received by a corresponding photodetectors, said output terminals being divided into n'' groups of terminals; a plurality n'' of shift registers, one associated with each group of output terminals and each having a number k of stages corresponding to the number of output terminals of its associated group thereof, the output terminals of such associated group thereof being connected individually to the stages of the associated shift register whereby information is presented in parallel to each shift register and each stage of each shift register having a read output terminal and said read output terminals of each shift register being connected together whereby a false read mode would occur in response to simultaneous signals at more than one read output terminal of such each shift register, and each shift register haviNg a command input terminal for inserting into the first stage thereof a binary command signal; clock input means connected to each shift register for shifting said binary command signal sequentially through the associated k stages correspondingly to gate the information of a photodetector output terminal to the corresponding read output terminal; and logic means associated with each shift register interconnecting command signals of each such shift register to the command input terminal of another shift register for inserting the binary command signal into such another shift register at a predetermined time.

Claim 16

In a character-recognition system, the combination of: a plurality of photodetectors arranged in a column simultaneously to receive light signals corresponding to an information column of the character-recognition system, said photodetectors presenting a plurality m of output terminals at which binary signals appear dependent upon the presence and absence of character information received by a corresponding photodetectors, said output terminals being divided into n'' groups of terminals; a plurality n'' of shift registers, one associated with each group of output terminals and each having a number k of stages corresponding to the number of output terminals of its associated group thereof, the output terminals of such associated group thereof being connected individually to the stages of the associated shift register whereby information is presented in parallel to each shift register and each stage of each shift register having a read output terminal and said read output terminals of each shift register being connected together whereby a false read mode would occur in response to simultaneous signals at more than one read output terminal of such each shift register, and each shift register haviNg a command input terminal for inserting into the first stage thereof a binary command signal; clock input means connected to each shift register for shifting said binary command signal sequentially through the associated k stages correspondingly to gate the information of a photodetector output terminal to the corresponding read output terminal; and logic means associated with each shift register interconnecting command signals of each such shift register to the command input terminal of another shift register for inserting the binary command signal into such another shift register at a predetermined time.

Claim 17

In a character-recognition system as defined in claim 12 wherein each said logic means is connected to the first k-l stages of its associated shift register.

Claim 18

In a character-recognition system as defined in claim 13 wherein each said logic means includes a NOR gate having the command signals of the corresponding k-l stages connected as inputs thereto.

Claim 19

In a character-recognition system as defined in claim 13 wherein each said logic means includes gate means connected with the kth stage of its corresponding shift register.

Claim 20

In a character-recognition system as defined in claim 12 wherein said logic means cause said n'' groups to be read sequentially.

Claim 21

In a character-recognition system as defined in claim 12 wherein said logic means cause stages of said n'' groups to be read alternately.