Integrated differential amplifier

Claim 2

A differential amplifier comprising first and second transistors arranged in a longtailed pair configuration having interconnected emitter electrodes, means for applying a signal to be amplified between the base electrodes of said transistors, a third transistor with its collector connected to said emitter electrodes, means connected to the base electrode of the third transistor for reducing the direct current flowing through said third transistor with increasing input signal intensity, a fourth transistor with its base electrode connected to the base electrode of the first transistor and with its collector electrode connected to the collector electrode of the first transistor, a fifth transistor with its base electrode connected to the base electrode of the second transistor and with its collector electrode connected to the collector electrode of the second transistor, and means connecting the emitter electrodes of said fourth and fifth transistors to first and second substantially equal emitter resistors, respectively.

Claim 3

A difference amplifier as claimed in claim 1, characterized in that said emitter resistors are connected to the collector electrode of a sixth transistor biased to convey a direCt current.

Claim 4

A difference amplifier as claimed in claim 2, characterized in that means are connected to the base electrode of the sixth transistor for cutting off this transistor for an input signal below a given intensity and for increasing the direct current through said transistor for an increasing input signal above said given intensity.

Claim 5

A difference amplifier as claimed in claim 1 further comprising means connected to the emitter electrode of the third transistor for generating a bias voltage for cutting off said transistor upon receipt of an input signal of a relatively large signal intensity.

Claim 6

A differential amplifier comprising first and second transistors connected as a first difference amplifier stage and having interconnected emitter electrodes, a pair of input terminals adapted to receive an input signal to be amplified and coupled respectively to the base electrodes of said first and second transistors, a source of supply voltage, a third transistor with its emitter-collector path connected individually in series with the emitter-collector paths of said first and second transistors across said voltage supply to form a direct current source for said transistors, means controlled by the input signal and coupled to the base of the third transistor for controlling the direct current flowing through said third transistor as an inverse function of the amplitude of the input signal, fourth and fifth transistors connected as a second difference amplifier stage, means connecting the base and collector of the fourth transistor to the base and collector, respectively, of the first transistor, means connecting the base and collector of the fifth transistor to the base and collector, respectively, of the second transistor, and means for biasing said fourth and fifth transistors at a level so that low amplitude signals are amplified primarily by said first and second transistors whereas high amplitude signals are amplified primarily by said fourth and fifth transistors.

Claim 7

A differential amplifier comprising first and second transistors connected as a first difference amplifier stage and having interconnected emitter electrodes, a pair of input terminals adapted to receive an input signal to be amplified and coupled respectively to the base electrodes of said first and second transistors, a source of supply voltage, a third transistor with its emitter-collector path connected individually in series with the emitter-collector paths of said first and second transistors across said voltage supply to form a direct current source for said transistors, means controlled by the input signal and coupled to the base of the third transistor for controlling the direct current flowing through said third transistor as an inverse function of the amplitude of the input signal, fourth and fifth transistors connected as a second difference amplifier stage, means connecting the base and collector of the fourth transistor to the base and collector, respectively, of the first transistor, means connecting the base and collector of the fifth transistor to the base and collector, respectively, of the second transistor, and means for biasing said fourth and fifth transistors at a level so that low amplitude signals are amplified primarily by said first and second transistors whereas high amplitude signals are amplified primarily by said fourth and fifth transistors.

Claim 8

A differential amplifier as claimed in claim 5 wherein said biasing means comprise first and second substantially equal resistors connected to the emitter electrodes of said fourth and fifth transistors, respectively.

Claim 9

A differential amplifier as claimed in claim 6 wherein the emitter resistors are connected in common to the collector of a sixth transistor having a DC bias applied to its base electrode thereby to pass a direct current.

Claim 10

A differential amplifier as claimed in claim 6 wherein the emitter resistors are connected in common to the collector of a sixth transistor having a base electrode controlled by the input signal for controlling the direct current flowing through said sixth transistor as a direct function of the amplitude of the input signal.

Claim 11

A differential amplifier as claimed in claim 7 further comprising means connecting the emitter-collector path of the sixth transistor individually in series with the emitter-collector paths of said fourth and fifth transistors across said voltage supply so that the sixth transistor acts as a current source for the fourth and fifth transistors.

Claim 12

A differential amplifier as claimed in claim 5 further comprising means controlled by the input signal for biasing said third transistor into cut-off upon receipt of an input signal above a given amplitude.

Claim 13

A differential amplifier as claimed in claim 5 further comprising sixth and seventh transistors connected as a third difference amplifier stage with their emitter-collector paths in series with the emitter-collector paths of the first and second transistors across said voltage supply, eighth and ninth transistors connected as a fourth difference amplifier stage with their emitter-collector paths in series with the emitter-collector paths of the fourth and fifth transistors across said voltage supply, means connecting the collector electrodes of said sixth and seventh transistors to the collector electrodes of the eighth and ninth transistors, respectively, and mEans connecting the base electrodes of said sixth and seventh transistors to a second pair of input terminals and to the base electrodes of said ninth and eighth transistors, respectively.