Method and apparatus to test electronic circuit assembly samples

Claim 2

Method to test sample electronic circuit assemblies having a plurality of numbered electrically accessible terminals which form input and output terminals therefor, comprising combining the numbered terminals of the samples which form input terminals into groups of not more than n terminals; connecting said groups of not more than n terminals in a connecting matrix so as to be fed in parallel with signals supplied on n input terminals of said matrix; generating 2n code combinations on n leads in a predetermined program and at a predetermined clock rate; applying to and storing the 2n code combinations in an intermediate storage means and applying the 2n code combinations over the connecting matrix to the terminals of the inputs of the sample; comparing the pulses applied to the input terminals and comparing the pulses appearing at the output terminals of said sample with a standard pulse combination sequence; and testing for coincidence between the standard pulse combination sequence and the pule combination sequence appearing at the output terminals of the sample and indicating, upon detection of noncoincidence, the pulse code combination temporarily stored in the intermediate storage means giving rise to the output resulting in noncoincidence.

Claim 3

Method according to claim 1, comprising the step of simultaneously applying the 2n code pulse combinations to a standard circuit assembly and to a test sample circuit; wherein the step of comparing the standard pulse combination sequences with the pulses appearing at the input and output of the sample comprises comparing the input and output pulses from the standard circuit with the pulses from the test sample.

Claim 4

Method according to claim 1, including the steps of a. changing the relative order of the numbered terminals in the groups of n terminals and thus the application of pulses from predetermined outputs of the code generator to some individual input terminals of the sample; b. counting the number of different combinations of output terminal pulses being stored; repeating the steps (a) and (b) with a variety of terminal groupings and selecting for further tests the grouping producing the lowest number of different output combinations.

Claim 5

Method according to claim 1, comprising the step of applying to the sample a test synchronizing signal before application of the 2n code combinations to set circuit elements in the sample which do not have a defined input state into a synchronized predetermined state.

Claim 6

Method according to claim 1, wherein prior to application of said 2n code combinations a start synchronizing signal is applied comprising a pulse train or group of pulses to set a combination of circuit elements in the sample in a predetermined combination of states.

Claim 7

Method according to claim 1, further comprising the step of first testing the sample for input and output short-circuit paths, and inhibiting application of code combinations to the sample which may generate short circuit currents.

Claim 8

Method according to claim 1, including the step of indicating, besides the code combination representative of non-coincidence, the pulse code combination within the program which last yielded coincidence.

Claim 9

Method according to claim 1, including the step of indicating, besides the code combination representative of non-coincidence, the pulsE code combination within the program which the code generator would next apply to the sample test.

Claim 10

Method according to claim 7, including storing the pulse code combination which still yielded coincidence and applying said stored coincidence combination and the non-coincident combination to an error analyzer.

Claim 11

Method according to claim 8, including the step of indicating, besides the code combination representative of non-coincidence, the pulse code combination within the program which last yielded coincident output.

Claim 12

Method according to claim 1, wherein the sequence of steps is repeated with the step of connecting the groups of n terminals over the connecting matrix to the pulse generator including a preliminary step of changing the interconnection circuit of the numbered terminals within the groups by changing the interconnecting circuit configuration of the connecting matrix to provide for different interconnection of the code generator with numbered input terminals, in groups, of the sample.

Claim 13

Test apparatus to test assembled electronic circuit samples, the circuit samples having a plurality of numbered electrically accessible terminals to form input and output terminals for the circuit samples, comprising a code generator (51) generating a code sequence of 2n pulses in a predetermined program; an intermediate storage device (55); a connecting matrix (52); a comparator (58); wherein the code generator (51) has a lesser number n of output terminals (I, II...XXV) than the terminals of the sample (1, 2...64) and the input terminals of the samples are grouped in groups of not more than n terminals each, and the connecting matrix connects said n output terminals in parallel to the terminals of said groups, the code generator and the input terminal groups being interconnected over the intermediate storage device (55) as well as over the connecting matrix (52); the output of the sample (57) being connected to one input of the comparator (58); means generating a standard comparison pulse code representative of the output pulses which should be obtained from the output of the sample (57) if the sample is free from defects or errors, said standard comparison code being connected to the other input of the comparator (58); and means (61, 62; 68) responsive to the output of the comparator indicating noncoincidence of the pulses derived from the output of the sample and the corresponding standard comparison code.

Claim 14

Test apparatus to test assembled electronic circuit samples, the circuit samples having a plurality of numbered electrically accessible terminals to form input and output terminals for the circuit samples, comprising a code generator (51) generating a code sequence of 2n pulses in a predetermined program; an intermediate storage device (55); a connecting matrix (52); a comparator (58); wherein the code generator (51) has a lesser number n of output terminals (I, II...XXV) than the terminals of the sample (1, 2...64) and the input terminals of the samples are grouped in groups of not more than n terminals each, and the connecting matrix connects said n output terminals in parallel to the terminals of said groups, the code generator and the input terminal groups being interconnected over the intermediate storage device (55) as well as over the connecting matrix (52); the output of the sample (57) being connected to one input of the comparator (58); means generating a standard comparison pulse code representative of the output pulses which should be obtained from the output of the sample (57) if the sample is free from defects or errors, said standard comparison code being connected to the other input of the comparator (58); and means (61, 62; 68) responsive to the output of the comparator indicating noncoincidence of the pulses derived from the output of the sample and the corresponding standard comparison code.

Claim 15

Apparatus according to claim 12, wherein the means generating the standard comparison pulse code comprises a standard circuit assembly known to be error free; means applying said code sequence from the code generator (51) to said standard circuit assembly; and means connected to the output terminals thereof, and receiving the outputs from said standard sample for applying them to said comparator.

Claim 16

Apparatus according to claim 12, wherein the means generating a standard comparison pulse code comprises; means (60) for reading the stored representation of output pulses obtained from a standard comparison circuit known to be error free and supplying therefrom a pulse sequence for application to said comparator.

Claim 17

Apparatus according to claim 12, further comprising controllable input means (53) connected to the connecting matrix, the controllable input means setting the transfer circuits of the connecting matrix to determine the interconnection between the respective outputs (I, II...XXV) of the code generator (51) to the sample (P1, ....P64).

Claim 18

Apparatus according to claim 15, wherein the controllable input means contorls the interconnecting paths of the connecting matrix from the code generator to selected inputs within the groups of input terminals of the sample.

Claim 19

Apparatus according to claim 12, including a short circuit test unit (90) connectable to selected terminals of the test sample (57) to pErmit testing of the sample for short circuit condition, and means (92) inhibiting application of pulses to the sample if the short circuit test indicates presence of a short circuit.

Claim 20

Apparatus according to claim 12, further comprising a connecting circuit interconnecting the test sample (57) with the connecting matrix (52) and the intermediate storage device (55), the connecting circuit comprising controllable circuit means (UL; UO; TL; TO) for preventing energization of certain terminals of said sample by pulses produced by said code generator.

Claim 21

Apparatus according to claim 12, further comprising output control means (67; 66) interconnected between the code generator (65) and the test sample (57), said output control means inhibiting change of output pulse from the code generator at more than one output terminal of the code generator, at any one time.

Claim 22

Apparatus according to claim 19, wherein the output control means comprises a counter (66) sequentially opening the output terminals of the code generator, in timed stepped sequence, and controlling the timing of transfer of output pulses from the code generator by strobing the output pulses thereof; and buffer storage means (51A) storing the strobed output pulses, to provide intermediate programming steps and prevent change of more than one output from the code generator at any one pulse period.

Claim 23

Apparatus as claimed in claim 12, wherein the connecting matrix comprises an X-Y interconnection array interconnecting selected output terminals (I, II...XXV) of the code generator (51) with selected terminals (P1, P2...P64) of the sample (57) with no two of said output terminals (I, II...XXV) being connected to the same selected terminals (P1, P2...P64) of the sample.

Claim 24

Apparatus according to claim 21, wherein the X-Y interconnection array is pre-wired.

Claim 25

Apparatus according to claim 21, wherein the X-Y interconnection array is programmable to provide for selectively changeable interconnection of the code generator (51) terminals with the sample (57) terminals.