US3810152A — Method and apparatus for conversion of a variable…

Claim 1

Independent Claim 317 words

An electrical circuit for converting a parameter to a time period comprising a power source having a voltage Es across its terminals, a low limit voltage divider means for establishing a low limit voltage, a high limit voltage divider means for establishing a high limit voltage and a parameter voltage divider means including a parameter sensing resistor for establishing a parameter voltage, each one of said voltage dividers being connected in parallel with the other of said voltage dividers across said power source, a low limit voltage comparator having one input terminal connected to the low limit voltage divider means to receive said low limit voltage and a second input terminal for receiving a ramp voltage, a high limit voltage comparator having one input terminal connected to said high limit voltage divider means to receive said high limit voltage and a second input terminal for receiving said ramp voltage, a parameter voltage comparator having one input terminal connected to said parameter voltage divider means to receive said ramp voltage, and a second input terminal for receiving said ramp voltage, a ramp voltage generator means connected to said voltage source for periodically generating a ramp voltage which starts at zero volts and increases toward the voltage across the terminals of said power source with increasing time, said low level comparator, said parameter comparator and said high level comparator each changing states in succession as the ramp voltage exceeds the output of the low level voltage divider, the parameter voltage divider and the high level voltage divider respectively to establish time periods between the change of state of said comparators, short duration pulse producing means connected to each of said low limit comparator, said parameter comparator, and to said high limit comparator for producing a pulse each time said comparators change state, and means for combining said pulses along a time base to produce a pulse position modulated signal.

Claim 2

Dependent Claim 317 words

An electrical circuit for converting a parameter to a time period comprising a power source having a voltage Es across its terminals, a low limit voltage divider means for establishing a low limit voltage, a high limit voltage divider means for establishing a high limit voltage and a parameter voltage divider means including a parameter sensing resistor for establishing a parameter voltage, each one of said voltage dividers being connected in parallel with the other of said voltage dividers across said power source, a low limit voltage comparator having one input terminal connected to the low limit voltage divider means to receive said low limit voltage and a second input terminal for receiving a ramp voltage, a high limit voltage comparator having one input terminal connected to said high limit voltage divider means to receive said high limit voltage and a second input terminal for receiving said ramp voltage, a parameter voltage comparator having one input terminal connected to said parameter voltage divider means to receive said ramp voltage, and a second input terminal for receiving said ramp voltage, a ramp voltage generator means connected to said voltage source for periodically generating a ramp voltage which starts at zero volts and increases toward the voltage across the terminals of said power source with increasing time, said low level comparator, said parameter comparator and said high level comparator each changing states in succession as the ramp voltage exceeds the output of the low level voltage divider, the parameter voltage divider and the high level voltage divider respectively to establish time periods between the change of state of said comparators, short duration pulse producing means connected to each of said low limit comparator, said parameter comparator, and to said high limit comparator for producing a pulse each time said comparators change state, and means for combining said pulses along a time base to produce a pulse position modulated signal.

Claim 3

Dependent Claim 34 words

The apparatus set forth in claim 1, wherein said short duration pulse producing means are one shot multivibrators and wherein said means for combining said pulses along a time base is an OR gate.

Claim 4

Dependent Claim 322 words

An electrical circuit for converting a parameter to a time period comprising a power source having a voltage Es across its terminals, a low limit voltage divider means for establishing a low limit voltage, a high limit voltage divider means for establishing a high limit voltage and a parameter voltage divider means including a parameter sensing resistor for establishing a parameter voltage, each one of said voltage dividers being connected in parallel with the other of said voltage dividers across said power source, a low limit voltage comparator having one input terminal connected to the low limit voltage divider means to receive said low limit voltage and a second input terminal for receiving a ramp voltage, a high limit voltage comparator having one input terminal connected to said high limit voltage divider means to receive said high limit voltage and a second input terminal for receiving said ramp voltage, a parameter voltage comparator having one input terminal connected to said parameter voltage divider means to receive said parameter voltage, and a second input terminal for receiving said ramp voltage, a ramp voltage generator means connected to said voltage source for periodically generating a ramp voltage which starts at zero volts and increases toward the voltage across the terminals of said power source with increasing time, said low level comparator, said parameter comparator and said high level comparator each changing states in succession as the ramp voltage exceeds the output of the low level voltage divider, the parameter voltage divider and the high level voltage divider respectively to establish time periods between the change of state of said comparators and means responsive to the change of state of said comparators for producing an increasing stepped voltage signal output, the first voltage step occurring when said low level comparator changes state, the second voltage step occurring when said parameter comparator changes state and the third step occurring when said high limit comparator changes state.

Claim 5

Dependent Claim 322 words

An electrical circuit for converting a parameter to a time period comprising a power source having a voltage Es across its terminals, a low limit voltage divider means for establishing a low limit voltage, a high limit voltage divider means for establishing a high limit voltage and a parameter voltage divider means including a parameter sensing resistor for establishing a parameter voltage, each one of said voltage dividers being connected in parallel with the other of said voltage dividers across said power source, a low limit voltage comparator having one input terminal connected to the low limit voltage divider means to receive said low limit voltage and a second input terminal for receiving a ramp voltage, a high limit voltage comparator having one input terminal connected to said high limit voltage divider means to receive said high limit voltage and a second input terminal for receiving said ramp voltage, a parameter voltage comparator having one input terminal connected to said parameter voltage divider means to receive said parameter voltage, and a second input terminal for receiving said ramp voltage, a ramp voltage generator means connected to said voltage source for periodically generating a ramp voltage which starts at zero volts and increases toward the voltage across the terminals of said power source with increasing time, said low level comparator, said parameter comparator and said high level comparator each changing states in succession as the ramp voltage exceeds the output of the low level voltage divider, the parameter voltage divider and the high level voltage divider respectively to establish time periods between the change of state of said comparators and means responsive to the change of state of said comparators for producing an increasing stepped voltage signal output, the first voltage step occurring when said low level comparator changes state, the second voltage step occurring when said parameter comparator changes state and the third step occurring when said high limit comparator changes state.

Claim 6

Dependent Claim 73 words

The apparatus set forth in claim 3 wherein said means responsive to the change of state of said comparators includes an operational amplifier having a resistance feedback path between its output and input terminals, the input terminal of said operational amplifier being connected through parallel conductive paths to the output terminals of said low limit comparator, said parameter comparator and said high level comparator, and each of said parallel paths including a resistor.

Claim 7

Dependent Claim 200 words

The apparatus set forth in claim 1 together with an analogue restoration system comprising a decoding ramp generator producing a decoding rAmp voltage increasing with time, an analogue output sampling circuit for sampling said decoding ramp voltage and providing for a period of time an output voltage equal to the decoding ramp voltage when sampled, a reference voltage source, a summing means for producing an error voltage which is the algebraic difference between the decoding ramp voltage and the reference voltage, an error sampling circuit for sampling the error voltage from said summing amplifier and holding said error voltage over a period of time, a feedback means connected from said error sampling circuit to said decoding ramp generator for changing the slope of the decoding ramp to reduce the error voltage signal, and control means which sequentially starts said ramp from zero volts at the time said low level comparator changes state, connects said analogue voltage sampling circuit to the output of said decoding ramp generator when said parameter comparator changes state, and which connects said error voltage sampling circuit to said summing amplifier when said high limit comparator changes state, said control means recycling and repeating its functions periodically.

Claim 8

Independent Claim 436 words

A method for creating a time ratio indication of resistance and reconstruction of a precise voltage indication of said resistance comprising simultaneously creating a parameter voltage proportional to an unknown resistance, a high limit voltage, and a low limit voltage, said low limit voltage and said high limit voltages establishing a voltage range within which said parameter voltage is expected to remain, creating a first ramp voltage which gradually increases at a substantially constant rate from below said low limit voltage to at least said high limit voltage, comparing said low limit voltage, said parameter voltage and said high limit voltage, with said first ramp voltage and producing a zero time delineating signal when said first ramp voltage equals said low limit voltage, a parameter time delineating signal when said first ramp voltage equals said parameter voltage, and a full scale time delineating signal when said first ramp voltage equals said high limit voltage, the time interval between said parameter time delineating signal and said zero time delineating signal, being proportional to the time interval between said full scale time delineating signal and zero time delineating signal, starting a second ramp voltage beginning at zero volts upon the occurrence of said zero time delineating signal, said second ramp voltage increasing at a predetermined constant rate, sampling and holding said second ramp voltage upon the occurrence of said parameter time delineating signal to produce an output voltage representing a precise voltage indication of said resistance comparing said second ramp voltage with a reference voltage and producing an error voltage which is the algebraic difference between said second ramp voltage and said reference voltage, sampling and holding said error voltage upon the occurrence of said full scale time delineating signal, using said sampled error voltage to change the rate of increase of said second ramp voltage to reduce said error voltage at the time of said full scale time delineating signal to zero, periodically repeating the creation of said first ramp voltage and comparison of said low limit voltage, said parameter voltage and said high limit voltage therewith and production of periodically recurring zero time delineating signal, parameter time delineating signal, and full scale delineating signal, periodically repeating the creation of said second ramp voltage upon the occurrence of each successive zero time delineating signal, periodically sampling and holding said second ramp voltage upon the occurrence of each successive parameter delineating time signal to produce an output voltage representing a precise voltage indication of said resistance, and periodically repeating the sampling and holding of said error signal upon the occurrence of each successive full scale time delineating signal.

Claim 9

Independent Claim 436 words

A method for creating a time ratio indication of resistance and reconstruction of a precise voltage indication of said resistance comprising simultaneously creating a parameter voltage proportional to an unknown resistance, a high limit voltage, and a low limit voltage, said low limit voltage and said high limit voltages establishing a voltage range within which said parameter voltage is expected to remain, creating a first ramp voltage which gradually increases at a substantially constant rate from below said low limit voltage to at least said high limit voltage, comparing said low limit voltage, said parameter voltage and said high limit voltage, with said first ramp voltage and producing a zero time delineating signal when said first ramp voltage equals said low limit voltage, a parameter time delineating signal when said first ramp voltage equals said parameter voltage, and a full scale time delineating signal when said first ramp voltage equals said high limit voltage, the time interval between said parameter time delineating signal and said zero time delineating signal, being proportional to the time interval between said full scale time delineating signal and zero time delineating signal, starting a second ramp voltage beginning at zero volts upon the occurrence of said zero time delineating signal, said second ramp voltage increasing at a predetermined constant rate, sampling and holding said second ramp voltage upon the occurrence of said parameter time delineating signal to produce an output voltage representing a precise voltage indication of said resistance comparing said second ramp voltage with a reference voltage and producing an error voltage which is the algebraic difference between said second ramp voltage and said reference voltage, sampling and holding said error voltage upon the occurrence of said full scale time delineating signal, using said sampled error voltage to change the rate of increase of said second ramp voltage to reduce said error voltage at the time of said full scale time delineating signal to zero, periodically repeating the creation of said first ramp voltage and comparison of said low limit voltage, said parameter voltage and said high limit voltage therewith and production of periodically recurring zero time delineating signal, parameter time delineating signal, and full scale delineating signal, periodically repeating the creation of said second ramp voltage upon the occurrence of each successive zero time delineating signal, periodically sampling and holding said second ramp voltage upon the occurrence of each successive parameter delineating time signal to produce an output voltage representing a precise voltage indication of said resistance, and periodically repeating the sampling and holding of said error signal upon the occurrence of each successive full scale time delineating signal.

Claim 10

Dependent Claim 328 words

An analogue restoration system for converting a time ratio indication of a parameter resistance to an analogue voltage precisely representing said parameter resistance, said system receiving successively repeating time signals including a zero time delineating signal, a parameter time delineating signal and a full scale time delineating signal, said full scale time delineating signal being spaced from said zero time delineating signal by a time interval representing a full scale resistance and said parameter time delineating signal being spaced from said zero time delineating signal by a time interval representing said parameter resistance, said analogue restoration system comprising a decoding ramp generator producing a decoding ramp voltage increasing with time, an analogue output sample and hold circuit means for sampling said decoding ramp voltage and providing an analogue output voltage substantially equal to the decoding ramp voltage when sampled over a period of time, a reference voltage source, a summing means for producing an error voltage which is the algebraic difference between the decoding ramp voltage and the reference voltage, an error sample and hold circuit means for sampling the error voltage from said summing amplifier and holding said error voltage over a period of time, a feedback circuit means connected from said error sample and hold circuit to said decoding ramp generator for changing the slope of the decoding ramp to reduce said error voltage, and control means responsive to said successively repeating time signals for sequentially starting said decoding ramp generator to produce said decoding ramp starting at zero volts upon the occurrence of said zero time delineating signal, connecting said analogue voltage sample and hold circuit means to the output of said decoding ramp generator upon the occurrence of said parameter time delineating signal and connecting said error voltage sample and hold circuit means to said summing means upon the occurrence of said full scale time delineating signal, said control means having reset means causing the control means to recycle and repeat its functions periodically.

Claim 11

Dependent Claim 328 words

An analogue restoration system for converting a time ratio indication of a parameter resistance to an analogue voltage precisely representing said parameter resistance, said system receiving successively repeating time signals including a zero time delineating signal, a parameter time delineating signal and a full scale time delineating signal, said full scale time delineating signal being spaced from said zero time delineating signal by a time interval representing a full scale resistance and said parameter time delineating signal being spaced from said zero time delineating signal by a time interval representing said parameter resistance, said analogue restoration system comprising a decoding ramp generator producing a decoding ramp voltage increasing with time, an analogue output sample and hold circuit means for sampling said decoding ramp voltage and providing an analogue output voltage substantially equal to the decoding ramp voltage when sampled over a period of time, a reference voltage source, a summing means for producing an error voltage which is the algebraic difference between the decoding ramp voltage and the reference voltage, an error sample and hold circuit means for sampling the error voltage from said summing amplifier and holding said error voltage over a period of time, a feedback circuit means connected from said error sample and hold circuit to said decoding ramp generator for changing the slope of the decoding ramp to reduce said error voltage, and control means responsive to said successively repeating time signals for sequentially starting said decoding ramp generator to produce said decoding ramp starting at zero volts upon the occurrence of said zero time delineating signal, connecting said analogue voltage sample and hold circuit means to the output of said decoding ramp generator upon the occurrence of said parameter time delineating signal and connecting said error voltage sample and hold circuit means to said summing means upon the occurrence of said full scale time delineating signal, said control means having reset means causing the control means to recycle and repeat its functions periodically.

Claim 12

Dependent Claim 39 words

The apparatus set forth in claim 7 wherein said control means includes a resettable counter means which advances one step upon the occurrence of each successive time signal and resets after each full scale time delineating signal is received.

Claim 13

Dependent Claim 260 words

The apparatus set forth in claim 7 wherein said decoding ramp generator includes an operational amplifier having input and output terminals, an integrating capacitor connected between the input and output terminal of said operational amplifier and a shunting circuit having a first switch means therein for opening and closing said shunting circuit connected between the input and output terminals of said operational amplifier, said analogue output sample and hold circuit means including a second switch means fo9 opening and closing said analogue output sample and hold circuit, said error sample and hold circuit means having a third switch means for opening and closing said error sample and hold circuit means, said control means including a resettable counter having a zero state and three successive count states, means for applying said time signals to said counter for successively changing the state of said counter through said three successive count states, means responsive to said counter in its first count state for opening said first switch in said shunting circuit of said decoding ramp generator to start said ramp generator, means responsive to said counter in its second count state for closing said second switch for a predetermined time interval and means responsive to said counter in its third count state for closing said third switch for a predetermined time interval, said reset means including means operative after said counter is in its third count state to cause said counter to reset to zero and to cause said means responsive to said counter in its first state to close said first switch.

Claim 14

Dependent Claim 108 words

The apparatus set forth in claim 9 wherein said means responsive to said counter in its first state is a flip-flop multivibrator having one output state which causes said first switch to open and a second output state which causes said first switch to close, said means responsive to said counter in its second state and said means responsive to said counter in its third state being first and second one shot multivibrators respectively, said first and second one shot multivibrators changing state in response to said counter reaching its second and third count states respectively and returning automatically to a normal initial state after predetermined time intervals.

Claim 15

Dependent Claim 108 words

The apparatus set forth in claim 10 wherein said means operative after said counter is in its third count state to cause said counter to reset to zero and to cause said means responsive to said counter in its first state to close said first switch includes a third one shot multivibrator which changes state when said second one shot multivibrator returns to its initial state after responding to said counter in its third state, and circuit means connecting the output of said third one shot multivibrator to said counter for resetting same to zero and to said flip-flop multivibrator for changing it to its second output state.

Claim 16

Dependent Claim 71 words

The apparatus set forth in claim 11 wherein said control means further includes an OR gate connected to said counter for controlling same, said OR gate having a pair of input terminals, one for receiving said time signals and the other connected to said third one shot multivibrator for receiving a reset signal therefrom, said OR gate responding sequentially to said time signals and said reset signal to actuate said counter.

Claim 17

Dependent Claim 30 words

The apparatus set forth in claim 7 wherein said feedback circuit means includes an operational amplifier in circuit with resistance means, and an integrating capacitor connected across said operational amplifier.

Claim 18

Dependent Claim 160 words

The apparatus set forth in claim 1 wherein said ramp generator means includes an operational amplifier having input and output terminals, an integrating capacitor, a shunting circuit having normally open circuit interrupting means therein, said integrating capacitor and said shunting circuit each being connected across the input and output terminals of said operational amplifier, means connecting said input terminal of said operational amplifier to the high voltage side of said power source, means connecting the output terminal of said operational amplifier to the second input terminals of each of said low limit voltage comparator, said high limit voltage comparator, and said parameter voltage comparator, and means responsive when said high limit voltage comparator changes state as the ramp voltage exceeds the output of said high limit voltage divider to close said shunting circuit interrupting means for a brief time interval and thus reduce the output of said ramp voltage generating means to zero for the beginning of a new cycle.

Claim 19

Dependent Claim 63 words

The apparatus set forth in claim 14 wherein said shunting circuit interrupting means is a solid state switch, and said means for closing said shunting circuit interrupting means includes a one shot multivibrator connected in circuit between said high limit voltage comparator and said solid state switch for producing a control pulse for actuating said solid state switch to close said shunting circuit.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1977-05-06	1977-11-05	1978-05-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1981-05-06	1981-11-05	1982-05-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1985-05-06	1985-11-05	1986-05-07	$7700.00	Window Closed / Lapsed

Method and apparatus for conversion of a variable resistance to a time modulated signal and for analogue restoration

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag