Position scaler (shifter) for computer arithmetic unit

Claim 2

A position scaler for a computer arithmetic unit for shifting position of a number of information bit signals, either right or left with blank information fill, according to right and left shift direction signals and shift selection signals providing the number of shifts required, said position scaler comprising: a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting when activated by its shift selection signal an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the leaSt significant bit position and vice versa, the output signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, each of said shift selection units comprising A number of inclusive logic gates and B number of conjunctive logic gates where A is equal to the number of information bit signals plus the number of shift positions following the unit and where B is twice A; said highest shift selection unit including; a first plurality of conjunctive gates all controlled by the concurrence of the activated right shift signal and a disabled highest shift selection signal and one connected to each of the information bit signals; a second plurality of conjunctive gates all controlled by the concurrence of the activated left shift signal and the activated highest shift selection signal and one connected to each of the information bit signals except the first information bit signal; a third plurality of conjunctive gates all controlled by an actuated right shift signal and an actuated highest shift selection signal and one connected to each of the lower order information bit signals less the number of shift positions performed by the highest shift selection unit; and a fourth plurality of conjunctive gates all controlled by an actuated left shift signal and a disabled highest shift selection signal and connected to each of the lower order information bit signals less the number of shift positions performed by the highest shift selection unit and the first information bit signal, the output signals of two conjunctive gates being directed to one inclusive logic gate according to a truth table of the eventual shifted or not shifted information bit signals; each of said lower shift selection units shifting in one direction only, one-half of its conjunctive logic gates having one input connected to its activated shift selection signal and one-half connected to its disabled shift selection signal, the output signals from two conjunctive gates being directed to one inclusive logic gate according to the truth table of the eventual shifted or not shifted information bit signals and each conjunctive gate selectively connected to the output signals from the inclusive logic gate of the previous higher shift selection unit, with the lowest shift selection unit providing an output for each of the number of information bit signals.

Claim 3

A position scaler as defined in claim 1 wherein both left and right shift direction signals are activated to actuate both said first and second number of conjunctive gates according to the information bit signals to form a circular shift thereby placing the lesser significant digits into more significant positions and vice versa without loss of information bits.

Claim 4

A position scaler as defined in claim 1 wherein the number of information bit signals shifted are equal to a power of two and said plurality of shift selection units are equal in number to the power of two.

Claim 5

A position scaler is described in claim 1 wherein the number of information bit signals shifted are equal to eight, said plurality of shift selection units are equal in number to three, the highest shift selection unit shifts the information bits four places and the lower shift selection unit shifts the information bit signals two and one places respectively.

Claim 6

A position scaler for a computer arithmetic unit for shifting position of a number of information bit signals, either right or left with blank information fill, said position scaler comprising: a selection unit activated by shifting instructions including a shift direction signal to generate right and left shift signals and shift selection signals, and a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power Of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the output signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, each of said shift selection units comprising A number of inclusive logic gates and B number of conjunctive logic gates where A is equal to the number of information bit signals plus the number of shift positions following the unit and where B is twice A; said highest shift selection unit connected to said selection unit and having the information bit signals and highest shift signals selectively directed to its logic gates, wherein its logic gates are distributed such that a first number of conjunctive gates, all controlled by the concurrence of the right shift signal and a disabled highest shift selection signal and one selectively connected to each of the information bit signals, is equal to the number of information bit signals controlled by the position scaler, a second number of conjunctive gates, all controlled by an activated left shift signal and an activated highest shift selection signal, is equal to one less than the number of information bit signals, a third number of conjunctive gates, all controlled by the right shift signal and an actuated highest shift selection signal, is equal to the number of information bit signals less the number of shift positions performed by the highest shift selection unit, and a fourth number of conjunctive logic gates, all controlled by an actuated left shift signal and a disabled shift selection signal, is equal to one less than the number of information bit signals less the number of shifts performed by the highest shift selection unit, the output signals of two conjunctive gates being directed to one inclusive logic gate according to a truth table of the eventual shifted or not shifted information bit signals; said lower shift selection units shifting in one direction only and having one input of its conjunctive logic gates each selectively connected to said selection unit to receive the shift selection signal and inverted counterpart activating the particular shift selection unit and having one input selectively connected to the output of the inclusive logic gates of the output of two conjunctive gates being directed to one inclusive logic gate according to a truth table of the eventual shifted or not shifted information bit signals and to the next highest shift selection unit in turn, wherein the logic gates in each of the lower shift selection units are distributed such that one-half is controlled by the shift selection signal and one-half by its inverted counterpart and all selectively controlled by the output signals from the previous next higher shift selection unit such that, when two conjunctive gates, one controlled by the shift selection signal and one by its inverted counterpart, are combined in one inclusive gate according to the truth table, all possible eventual shift positions are covered, with the lowest shift selection units providing an output for each of the number of information bit signals.

Claim 7

A position scaler for a computer arithmetic unit for shifting position of a number of information bit signals, either right or left with blank information fill, said position scaler comprising: a selection unit activated by shifting instructions including a shift direction signal to generate right and left shift signals and shift selection signals, and a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power Of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the output signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, each of said shift selection units comprising A number of inclusive logic gates and B number of conjunctive logic gates where A is equal to the number of information bit signals plus the number of shift positions following the unit and where B is twice A; said highest shift selection unit connected to said selection unit and having the information bit signals and highest shift signals selectively directed to its logic gates, wherein its logic gates are distributed such that a first number of conjunctive gates, all controlled by the concurrence of the right shift signal and a disabled highest shift selection signal and one selectively connected to each of the information bit signals, is equal to the number of information bit signals controlled by the position scaler, a second number of conjunctive gates, all controlled by an activated left shift signal and an activated highest shift selection signal, is equal to one less than the number of information bit signals, a third number of conjunctive gates, all controlled by the right shift signal and an actuated highest shift selection signal, is equal to the number of information bit signals less the number of shift positions performed by the highest shift selection unit, and a fourth number of conjunctive logic gates, all controlled by an actuated left shift signal and a disabled shift selection signal, is equal to one less than the number of information bit signals less the number of shifts performed by the highest shift selection unit, the output signals of two conjunctive gates being directed to one inclusive logic gate according to a truth table of the eventual shifted or not shifted information bit signals; said lower shift selection units shifting in one direction only and having one input of its conjunctive logic gates each selectively connected to said selection unit to receive the shift selection signal and inverted counterpart activating the particular shift selection unit and having one input selectively connected to the output of the inclusive logic gates of the output of two conjunctive gates being directed to one inclusive logic gate according to a truth table of the eventual shifted or not shifted information bit signals and to the next highest shift selection unit in turn, wherein the logic gates in each of the lower shift selection units are distributed such that one-half is controlled by the shift selection signal and one-half by its inverted counterpart and all selectively controlled by the output signals from the previous next higher shift selection unit such that, when two conjunctive gates, one controlled by the shift selection signal and one by its inverted counterpart, are combined in one inclusive gate according to the truth table, all possible eventual shift positions are covered, with the lowest shift selection units providing an output for each of the number of information bit signals.

Claim 8

A position scaler as defined in claim 5 wherein both left and right shift direction signals are activated to actuate both said first and second number of conjunctive gates according to the information bit signals to form a circular shift thereby placing the lesser significant digits into more significant positions and vice versa without loss of information bits.

Claim 9

A position scaler as defined in claim 5 wherein the number of information bit signals shifted are equal to eight, said plurality of shift selection units are equal in number to three, the highest shift selection unit shifts the information bits four places and the lower shift selection unit shifts the information bit signals two and one places respectively.

Claim 10

A position scaler for a computer arithmetic unit for shifting eIght information bit signals, either right or left with blank information fill or circular, said position scaler comprising: a shift selection unit activated by shifting instructions including a shift right and a shift left direction signal and shift selection signals; a shift by four shift selection unit including twenty-two conjunctive logic gates having an input selectively connected to the information bit signals and having a second input of eight of these conjunctive logic gates controlled by a first signal generated by said shift selection unit comprising the concurrence of the shift right direction signal and an inverted shift by four selection signal, seven conjunctive logic gates controlled by a second signal generated by said shift selection unit comprising the concurrence of the shift left direction signal and a shift by four selection signal, four conjunctive logic gates controlled by a third signal generated by said shift selection unit comprising the concurrence of the shift right direction signal and the shift by four selection signal, and three conjunctive logic gates controlled by a fourth signal generated by said shift selection unit comprising the concurrence of the shift left direction signal and the inverted shift by four selection signal, the output of two conjunctive gates being selectively connected to an input to a two input inclusive logic gate; a shift by two shift selection unit shifting in one direction only and including eighteen conjunctive logic gates, nine comprising one group having a first input connected to a shift by two selection signal and nine comprising a second group having a first input connected to an inverted shift by two selection signal, and a second input selectively controlled by the output of the inclusive logic gates of the shift by four unit, the output of two conjunctive gates, one from each group, being selectively connected to an input of a two input inclusive logic gate; and a shift by one shift selection unit shifting in one direction only and including sixteen conjunctive logic gates, eight comprising one cluster having a first input connected to a shift by one selection signal and eight comprising a second cluster having a first input connected to an inverted shift by one selection signal, and a second input selectively controlled by the output of the inclusive logic gate of the shift by two unit, the output of two conjunctive gates, one from each cluster, being selectively connected to an input of a two input inclusive logic gate, the output of the inclusive logic gates being the shifted bit information signals; wherein each of the conjunctive gates in each of the shift selection units are selectively connected to its inclusive logic gates by using a truth table showing the position of the information bit signal after the shift selection unit according to an actuated or not shift selection signal and wherein a circular shift is performed by activating both shift right and shift left direction signals along with shift selection signals.

Claim 11

A position scaler for a computer arithmetic unit for shifting eIght information bit signals, either right or left with blank information fill or circular, said position scaler comprising: a shift selection unit activated by shifting instructions including a shift right and a shift left direction signal and shift selection signals; a shift by four shift selection unit including twenty-two conjunctive logic gates having an input selectively connected to the information bit signals and having a second input of eight of these conjunctive logic gates controlled by a first signal generated by said shift selection unit comprising the concurrence of the shift right direction signal and an inverted shift by four selection signal, seven conjunctive logic gates controlled by a second signal generated by said shift selection unit comprising the concurrence of the shift left direction signal and a shift by four selection signal, four conjunctive logic gates controlled by a third signal generated by said shift selection unit comprising the concurrence of the shift right direction signal and the shift by four selection signal, and three conjunctive logic gates controlled by a fourth signal generated by said shift selection unit comprising the concurrence of the shift left direction signal and the inverted shift by four selection signal, the output of two conjunctive gates being selectively connected to an input to a two input inclusive logic gate; a shift by two shift selection unit shifting in one direction only and including eighteen conjunctive logic gates, nine comprising one group having a first input connected to a shift by two selection signal and nine comprising a second group having a first input connected to an inverted shift by two selection signal, and a second input selectively controlled by the output of the inclusive logic gates of the shift by four unit, the output of two conjunctive gates, one from each group, being selectively connected to an input of a two input inclusive logic gate; and a shift by one shift selection unit shifting in one direction only and including sixteen conjunctive logic gates, eight comprising one cluster having a first input connected to a shift by one selection signal and eight comprising a second cluster having a first input connected to an inverted shift by one selection signal, and a second input selectively controlled by the output of the inclusive logic gate of the shift by two unit, the output of two conjunctive gates, one from each cluster, being selectively connected to an input of a two input inclusive logic gate, the output of the inclusive logic gates being the shifted bit information signals; wherein each of the conjunctive gates in each of the shift selection units are selectively connected to its inclusive logic gates by using a truth table showing the position of the information bit signal after the shift selection unit according to an actuated or not shift selection signal and wherein a circular shift is performed by activating both shift right and shift left direction signals along with shift selection signals.

Claim 12

A logical shifting device for binary information bit signals for shifting position of a number of the information bit signals, either right or left or in a circular mode according to right and left shift direction signals, and shift selection signals providing the number of shifts required, said shifting device comprising a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection unit each progressively shifting, when activated by its shift selection signal, an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the output signals from the shift selection unit being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, each of said sHift selection units comprising a number of conjunctive logic gates equal to twice the number of information bit signals plus the number of shift positions following the unit, with an input to the conjunctive logic gates of the highest shift selection unit being connected to receive the information bit signals and selectively controlled by the concurrence of the activated left shift signal together with the activated or disabled shift selection signal for the highest shift selection unit or the activated right shift signal together with the activated or disabled highest shift selection signal, said conjunctive logic gates of the lower shift selection units selectively controlled by the activated or disabled shift selection signals for its associated shift selection unit, and each of said shift selection units including means including a truth table to selectively connect the output signals from the higher shift selection unit to an input to the conjunctive logic gates of the next lower shift selection unit, said shift selection units other than the highest shift selection unit shifting in one direction only with a circular mode shift performed by activating both left and right shift direction signals, the output of the lowest shift selection unit being the shifted bit signals.

Claim 13

A logical shifting device for binary information bit signals for shifting position of a number of the information bit signals, either right or left or in a circular mode according to right and left shift direction signals, and shift selection signals providing the number of shifts required, said shifting device comprising a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection unit each progressively shifting, when activated by its shift selection signal, an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the output signals from the shift selection unit being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, each of said sHift selection units comprising a number of conjunctive logic gates equal to twice the number of information bit signals plus the number of shift positions following the unit, with an input to the conjunctive logic gates of the highest shift selection unit being connected to receive the information bit signals and selectively controlled by the concurrence of the activated left shift signal together with the activated or disabled shift selection signal for the highest shift selection unit or the activated right shift signal together with the activated or disabled highest shift selection signal, said conjunctive logic gates of the lower shift selection units selectively controlled by the activated or disabled shift selection signals for its associated shift selection unit, and each of said shift selection units including means including a truth table to selectively connect the output signals from the higher shift selection unit to an input to the conjunctive logic gates of the next lower shift selection unit, said shift selection units other than the highest shift selection unit shifting in one direction only with a circular mode shift performed by activating both left and right shift direction signals, the output of the lowest shift selection unit being the shifted bit signals.