Digital data processing apparatus

Claim 2

A digital data processing apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; a set of counters respectively corresponding to different stages of the shift register; count controlling means connected to said shift register and said counters and operative to cause each counter to count out of a sequence of successive occasions only those occasions on which there occurs in respect of the corresponding stage a given condition whose occurrence or non-occurrence on each of said occasions is dependent on the state of the stage on that occasion; and signalling means connected to said counters and comprising storage means for storing temporarily a binary word the digits of which correspond respectively to said counters and each digit of which has a first value or a second value according to whether or not the count for the corresponding stage has reached a given value; and signal generating means operative in response to the presence in said storage means of a binary word of which at least one of the digits has said first value to generate a signal whose form indicates the ordinal number of at least one stage for which the count has reached said given value.

Claim 3

An apparatus according to claim 1, further comprising means for generating a train of regularly recurrent clock pulses, and means for applying the clock pulses to the shift register so as to determine the instants at which the states of its stages can change.

Claim 4

An apparatus according to claim 2, in which said count controlling means is operative so that said given condition is the coincidence of the state of the relevant stage with the current state of a binary signal applied to a terminal of the count controlling means.

Claim 5

An apparatus according to claim 3, further comprising sampling means operative in response to the application of the clock pulses to generate first and second binary signals respectively corresponding to first and second input signals applied to the sampling means, the state of each binary signal between two consecutive ones of the instants at which the states of stages of the shift register can change being dependent on the polarity of the corresponding input signal at the earlier of these instants, and means for applying said first and second binary signals respectively to the input of the shift register and to said terminal of the gating means.

Claim 6

AN apparatus according to claim 2, further comprising means for applying the clock pulses to the count controlling means so as to determine the successive occasions of said sequence.

Claim 7

An apparatus according to claim 1, further comprising control means operable repeatedly to restore all the counters to a condition of zero count and thereby cause the apparatus to operate in repeated cycles each corresponding to one sequence of occasions.

Claim 8

An apparatus according to claim 6, further comprising means operable to cause the control means to operate in response to the reaching of said given value by the count for any of said stages.

Claim 9

An apparatus according to Claim 7, in which there is provided means for causing said storage means to take in at the end of each cycle a binary word indicating for which of said stages the count has reached said given value during that cycle, and said signal generating means is operative to generate for each cycle during which the count has reached said given value for any of said stages a signal whose form indicates the ordinal number of only one stage for which the count has reached said given value.

Claim 10

An apparatus according to claim 8, in which said signal generating means is operative to generate a train of pulses whose repetition frequency is inversely proportional to the cardinal number corresponding to said ordinal number.

Claim 11

An apparatus according to claim 6, further comprising means for causing the control means to operate in response to the elapsing of a given time from a previous operation of the control means.

Claim 12

An apparatus according to claim 10, further comprising means operable to terminate said sequence of occasions for any cycle in response to the reaching of said given value by the count for any of said stages before the elapsing of said given time.

Claim 13

An apparatus according to Claim 11, in which there is provided means for causing said storage means to take in at the end of each cycle a binary word indicating for which of said stages the count has reached said given value during that cycle, and said signal generating means is operative to generate for each cycle during which the count has reached said given value for any of said stages a signal whose form indicates the ordinal number of only one stage for which the count has reached said given value.

Claim 14

An apparatus according to claim 12, in which said signal generating means is operative to generate a train of pulses whose repetition frequency is inversely proportional to the cardinal number corresponding to said ordinal number.

Claim 15

An apparatus according to claim 10, in which there is provided means for causing said storage means to take in for each of a sequence of instants in each cycle a binary word indicating for which of said stages the count has reached said given value at that instant, and said signal generating means is operative to generate during each cycle a sequence of signals respectively corresponding to said sequence of instants and each having a form indicating the ordinal number of any and every one of said stages for which the count has reached said given value at the corresponding one of said instants.

Claim 16

An apparatus according to Claim 14, further comprising display means operative during each cycle in response to the application of said sequence of signals to provide a display of the information taken into said storage means for at least that part of said sequence of instants for which the count for any of said stages may have reached said given value.

Claim 17

A digital data processing apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; means for generating a train of regularly recurrent clock pulses; means for applying the clock pulses to the shift register so as to determine the instants at which the states of its stages can change; a set of counters respectively corresponding to different stAges of the shift register; gating means operative to cause each counter to count out of a sequence of successive occasions only those occasions on which there occurs in respect of the corresponding stage a coincidence between the state of the stage and the current state of a binary signal applied to a terminal of the gating means; sampling means operative in response to the application of the clock pulses to generate first and second binary signals respectively corresponding to first and second input signals applied to the sampling means, the state of each binary signal between two consecutive ones of the instants at which the states of stages of the shift register can change being dependent on the polarity of the corresponding input signal at the earlier of these instants; means for applying said first and second binary signals respectively to the input of the shift register and to said terminal of the gating means; control means operative repeatedly to restore all the counters to a condition of zero count and thereby cause the apparatus to operate in repeated cycles each corresponding to one sequence of occasions; means operative to terminate the sequence of occasions for any cycle in response to the reaching of a given value by the count for any of said stages; a pattern register operative to take in at the end of each cycle information indicating for which of said stages the count has reached said given value during that cycle and to store that information temporarily; and means operative in response to the information stored by the pattern register to generate for each cycle during which the count has reached said given value for any of said stages a signal whose form indicates the ordinal number of a stage for which the count has reached said given value.

Claim 18

A digital data processing apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; means for generating a train of regularly recurrent clock pulses; means for applying the clock pulses to the shift register so as to determine the instants at which the states of its stages can change; a set of counters respectively corresponding to different stAges of the shift register; gating means operative to cause each counter to count out of a sequence of successive occasions only those occasions on which there occurs in respect of the corresponding stage a coincidence between the state of the stage and the current state of a binary signal applied to a terminal of the gating means; sampling means operative in response to the application of the clock pulses to generate first and second binary signals respectively corresponding to first and second input signals applied to the sampling means, the state of each binary signal between two consecutive ones of the instants at which the states of stages of the shift register can change being dependent on the polarity of the corresponding input signal at the earlier of these instants; means for applying said first and second binary signals respectively to the input of the shift register and to said terminal of the gating means; control means operative repeatedly to restore all the counters to a condition of zero count and thereby cause the apparatus to operate in repeated cycles each corresponding to one sequence of occasions; means operative to terminate the sequence of occasions for any cycle in response to the reaching of a given value by the count for any of said stages; a pattern register operative to take in at the end of each cycle information indicating for which of said stages the count has reached said given value during that cycle and to store that information temporarily; and means operative in response to the information stored by the pattern register to generate for each cycle during which the count has reached said given value for any of said stages a signal whose form indicates the ordinal number of a stage for which the count has reached said given value.

Claim 19

An apparatus according to claim 16, in which said signal generating means is operative to generate a train of pulses whose repetition frequency is inversely proportional to the cardinal number corresponding to said ordinal number.

Claim 20

An apparatus according to claim 17, in which said signal generating means and said clock pulse generating means are operative so that the product of said repetition frequency and said cardinal number is directly proportional to the repetition frequency of the clock pulses.

Claim 21

An apparatus according to claim 16, further comprising means for applying the clock pulses to the gating means so as to determine the successive occasions of said sequence for each cycle.

Claim 22

A digital data processing apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; a set of counters respectively corresponding to different stages of the shift register; count controlling means connected to said shift register and said counters and operative to cause each counter to count out of a sequence of successive occasions only those occasions on which there occurs in respect of the corresponding stage a given condition whose occurrence or non-occurrence on each of said occasions is dependent on the state of the stage on that occasion; means for repeatedly restoring all the counters to a condition of zero count and thereby causing the apparatus to operate in repeated cycles; first storage means for storing temporarily a binary word the digits of which correspond respectively to said counters; means for operating said first storage means so that it takes in for each of a sequence of instants in each cycle a binary word each digit of which has a first value or a second value according to whether or not the count for the corresponding stage has reached a given value at that instant; comparison means for comparing first and second binary words the digits of each of which correspond respectively to said counters and for generating a further binary word the digits of which correspond respectively to said counters ane each digit of which has one or other of two values according tO whether or not these are satisfied all three conditions that a. the corresponding digit of said first binary word has said first value, b. the corresponding digit of said second binary word has said second value, and c. the position of the digit is separated from any digit position for which the digit of said second binary word has said first value by at least one digit position for which the digit of said first binary word has said second value; means for causing said comparison means to operate one for each instant of said sequence with said first binary word being the binary word taken in by said first storage means for that instant and with said second binary word being a binary word taken in by said first storage means for the preceding instant of said sequence and subsequently derived from said first storage means; second storage means for storing temporarily a binary word the digits of which correspond respectively to said counters; means for operating said second storage means so that it takes in for each instant of said sequence the further binary word generated by the operation of said comparison means for that instant; and signal generating means operative in response to the presence in said second storage means of a binary word of which at least one of the digits has said one of said two values to generate a signal whose form indicates the ordinal number of at least one stage of the shift register corresponding to a digit of that binary word which has said one of said two values.

Claim 23

A digital data processing apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; a set of counters respectively corresponding to different stages of the shift register; count controlling means connected to said shift register and said counters and operative to cause each counter to count out of a sequence of successive occasions only those occasions on which there occurs in respect of the corresponding stage a given condition whose occurrence or non-occurrence on each of said occasions is dependent on the state of the stage on that occasion; means for repeatedly restoring all the counters to a condition of zero count and thereby causing the apparatus to operate in repeated cycles; first storage means for storing temporarily a binary word the digits of which correspond respectively to said counters; means for operating said first storage means so that it takes in for each of a sequence of instants in each cycle a binary word each digit of which has a first value or a second value according to whether or not the count for the corresponding stage has reached a given value at that instant; comparison means for comparing first and second binary words the digits of each of which correspond respectively to said counters and for generating a further binary word the digits of which correspond respectively to said counters ane each digit of which has one or other of two values according tO whether or not these are satisfied all three conditions that a. the corresponding digit of said first binary word has said first value, b. the corresponding digit of said second binary word has said second value, and c. the position of the digit is separated from any digit position for which the digit of said second binary word has said first value by at least one digit position for which the digit of said first binary word has said second value; means for causing said comparison means to operate one for each instant of said sequence with said first binary word being the binary word taken in by said first storage means for that instant and with said second binary word being a binary word taken in by said first storage means for the preceding instant of said sequence and subsequently derived from said first storage means; second storage means for storing temporarily a binary word the digits of which correspond respectively to said counters; means for operating said second storage means so that it takes in for each instant of said sequence the further binary word generated by the operation of said comparison means for that instant; and signal generating means operative in response to the presence in said second storage means of a binary word of which at least one of the digits has said one of said two values to generate a signal whose form indicates the ordinal number of at least one stage of the shift register corresponding to a digit of that binary word which has said one of said two values.

Claim 24

An apparatus according to claim 20, further comprising means for providing information indicating the ordinal number of any instant in said sequence for which the operation of said comparison means generates a further binary word of which at least one of the digits has said one of said two values.

Claim 25

A digital data processing apparatus for comparing two binary signals, said apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; means for operating said shift register so that it stores temporarily, in respect of each a series of regularly recurrent instants, a binary word the digits of which correspond, in the sequence of said stages, to the states of a first one of the two binary signals at times earlier by successively greater amounts than the relevant one of said series of instants; means for effecting a sequence of comparison operations in each of which the state of the second of the two binary signals is compared with each of the digits of said binary word; means for counting the results of the comparisons separately for each digit position of said binary word; and signalling means for generating a signal in response to the reaching of a given value by the count for any one of the digit positions of said binary word, said signalling means comprising means causing the signal to have a form indicating for which of said digit positions the count first reached said given value.

Claim 26

A digital data processing apparatus for comparing two binary signals, said apparatus comprising: a binary shift register having a serial input and comprising a set of serially connected stages; means for operating said shift register so that it stores temporarily, in respect of each a series of regularly recurrent instants, a binary word the digits of which correspond, in the sequence of said stages, to the states of a first one of the two binary signals at times earlier by successively greater amounts than the relevant one of said series of instants; means for effecting a sequence of comparison operations in each of which the state of the second of the two binary signals is compared with each of the digits of said binary word; means for counting the results of the comparisons separately for each digit position of said binary word; and signalling means for generating a signal in response to the reaching of a given value by the count for any one of the digit positions of said binary word, said signalling means comprising means causing the signal to have a form indicating for which of said digit positions the count first reached said given value.

Claim 27

An apparatus according to claim 22, further comprising: means for repeatedly restoring said counting means to a condition of zero count for all digit positions of said binary word and thereby causing the apparatus to operate in repeated cycles; and means for terminating the sequence of comparison operations for any cycle in response to the reaching of said given value by the count for any of the digit positions of said binary word.

Claim 28

An apparatus according to claim 22, in which said means for operating said shift register comprises: means for applying said first one of the two binary signals continuously to said serial input of the shift register; means for generating a train of regularly recurrent clock pulses; and means for applying the clock pulses to the shift register so as to determine the instants at which the states of its stages can change.