Apparatus for the generation of bessel function signals

Claim 1

Apparatus for the generation of Bessel function signals J (z) of the first kind, of constant argument z and successive integral order Nu , comprising: a first signal source capable of generating signals of arbitrary amplitude J (z), where z is a constant; means connectable to the signal source for multiplying the values of J (z) by the quantity (2 Nu /z); a second signal source capable of generating signals of amplitude J 1(z); an inverter connected to, and for inverting a signal at, the output of the second signal source; the transit time of the J (z) signal traversing the multiplying means being substantially equal to the transit time of the J 1(z) signal traversing the inverter; the apparatus further comprising: a summing circuit, whose two inputs are the output of the multiplying means, (2 Nu /z) J (z), and the output of the inverter, -J 1(z), the output of the summing circuit thereby being 2 Nu /z J (z) - J 1(z), which is equal to J 1.

Claim 9

The apparatus for the generation of a sequence of Bessel function signals J (2j), of the first kind, of constant argument 2j and successive integral order Nu , comprising: a first shift register, having N stages, for shifting N bits; a second shift register, also having N stages, for shifting N bits, and whose output is connected to the input of the first shift register; the function of the first and second shift registers being to store and reorder signal samples in binary form to be used in a succeeding Bessel sequence; a first switching means, connected to the first shift register, for inserting an initial binary number into it; a second switching means, connected to the second shift register, for inserting an initial binary number into it; a third switching means, connected to the output stages of the first shift register; an accumulator having as one sets of inputs, the binary bits from the second shift register which correspond to the least significant digits, and as another set of inputs the least significant digits from the first shift register which however are shifted j-1 bits away from the least significant digit by the third switching means; a third shift register, whose input stages are connected to the output of the accumulator and whose output is connected to the input of the second shift register, facilitating transfer of signal samples from the accumulator to the second shift register; a Nu register which keeps track of the number Nu ; a fourth switching means, connected to the Nu register, for inserting the number Nu into it; a clock and timing control, connected to, and for controlling the flow of the binary bits in, the three shift registers and the accumulator; the clock and timing control also having an input from the Nu register; and a logic level source, which develops bilevel voltages, connected to, and which feeds the proper bilevel voltage to, the first, second, third and fourth switching means and the clock and timing control; the output of the Nu register causing the second shift register to discharge its contents into the accumulator Nu times simultaneously with the subtraction of the contents of the first shift register, the result of the two operations resulting in a binary number which is fed into the third shift register and then into the second shift register.

Claim 10

The apparatus for the generation of a sequence of Bessel function signals J (2j), of the first kind, of constant argument 2j and successive integral order Nu , comprising: a first shift register, having N stages, for shifting N bits; a second shift register, also having N stages, for shifting N bits, and whose output is connected to the input of the first shift register; the function of the first and second shift registers being to store and reorder signal samples in binary form to be used in a succeeding Bessel sequence; a first switching means, connected to the first shift register, for inserting an initial binary number into it; a second switching means, connected to the second shift register, for inserting an initial binary number into it; a third switching means, connected to the output stages of the first shift register; an accumulator having as one sets of inputs, the binary bits from the second shift register which correspond to the least significant digits, and as another set of inputs the least significant digits from the first shift register which however are shifted j-1 bits away from the least significant digit by the third switching means; a third shift register, whose input stages are connected to the output of the accumulator and whose output is connected to the input of the second shift register, facilitating transfer of signal samples from the accumulator to the second shift register; a Nu register which keeps track of the number Nu ; a fourth switching means, connected to the Nu register, for inserting the number Nu into it; a clock and timing control, connected to, and for controlling the flow of the binary bits in, the three shift registers and the accumulator; the clock and timing control also having an input from the Nu register; and a logic level source, which develops bilevel voltages, connected to, and which feeds the proper bilevel voltage to, the first, second, third and fourth switching means and the clock and timing control; the output of the Nu register causing the second shift register to discharge its contents into the accumulator Nu times simultaneously with the subtraction of the contents of the first shift register, the result of the two operations resulting in a binary number which is fed into the third shift register and then into the second shift register.