Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
235 words
A radio receiver squelch circuit with time constant controlled by signal level comprising, in combination, a first and a second input gate means, signal voltage divider means for feeding rectified signal noise of a common incoming radio signal at respective high and low levels to said first and second input gate means to render said first input gate means operative at a lower input signal level than said second input gate means, a high output level gate means and a low output level gate means, the distinctive outputs of said first and second input gate means being fed, respectively, to said high and low output level gate means, the output of said high output level gate means being operative to squelch the received radio signal, a source of DC supply voltage for energizing each of said gate means, the output of said first input gate means including an RC time delay circuit operative to be charged to said supply voltage upon the feeding of a noise signal of any level to the input of said first input gate means, the output of said second input gate means comprising a series resistor circuit operative to be connected in parallel with said RC time delay circuit upon the feeding of a noise signal to said first and second input gate means providing an input level to said second input gate means above a certain minimum threshold value.
Claim 2
Dependent Claim
235 words
A radio receiver squelch circuit with time constant controlled by signal level comprising, in combination, a first and a second input gate means, signal voltage divider means for feeding rectified signal noise of a common incoming radio signal at respective high and low levels to said first and second input gate means to render said first input gate means operative at a lower input signal level than said second input gate means, a high output level gate means and a low output level gate means, the distinctive outputs of said first and second input gate means being fed, respectively, to said high and low output level gate means, the output of said high output level gate means being operative to squelch the received radio signal, a source of DC supply voltage for energizing each of said gate means, the output of said first input gate means including an RC time delay circuit operative to be charged to said supply voltage upon the feeding of a noise signal of any level to the input of said first input gate means, the output of said second input gate means comprising a series resistor circuit operative to be connected in parallel with said RC time delay circuit upon the feeding of a noise signal to said first and second input gate means providing an input level to said second input gate means above a certain minimum threshold value.
Claim 3
Dependent Claim
37 words
A radio receiver squelch circuit as defined in claim 1, wherein said first and second input gate means and said high output level gAte means and said low output level gate means each comprises a NAND gate.
Claim 4
Dependent Claim
59 words
A radio receiver squelch circuit as defined in claim 2, wherein the output of said first input gate is fed directly to the inputs of said high output level gate through a first diode, and wherein the output of said second input gate is fed directly to the inputs of said low output level gate through a second diode.
Claim 5
Dependent Claim
42 words
A radio receiver squelch circuit as defined in claim 3, wherein said series resistor circuit comprises a diode and a resistor connected in series between the output of said low output level gate and the inputs of said high output level gate.
Claim 6
Dependent Claim
94 words
A radio receiver squelch circuit as defined in claim 4, including a second RC time-delay circuit in the output of said second input gate and having a substantially smaller time constant than said first mentioned RC time-delay circuit, said last mentioned time-delay circuit serving as a memory device preventing said high and low output level gates becoming deactuated at the same time upon discontinuance of signal noise, and thereby providing enough time for said first mentioned RC time-delay circuit parallel-connected with said series resistor to control the output of said high output level gate.
Claim 7
Dependent Claim
33 words
A radio receiver squelch circuit as defined in claim 5, wherein said signal voltage divider means comprises a potentiometer for variably adjusting the difference in input noise level to said second input gate.