Variable time ratio control having speed potentiometer failure protection

Claim 2

A control for supplying variable duty cycle pulses from an electrical power source to a load including, in combination, means for providing a succession of control pulses, means including a speed potentiometer for selectively varying the duty cycle of said control pulses, a power switch regulated by said control pulses for connecting said power source to said load, potentiometer failure detecting means for generating a potentiometer failure signal when the circuit through said speed potentiometer is open, and means responsive to said potentiometer failure signal for overriding said duty cycle varying means and reducing the duty cycle of said control pulses.

Claim 3

A control in accordance with claim 1 wherein said potentiometer failure detecting means includes transistor means for generating said potentiometer failure signal and being arranged and connected to be in a first operating state wherein it generates said potentiometer failure signal, and means including a circuit completed through said speed potentiometer for biasing said transistor means to a second operating state, whereby said potentiometer failure signal is only generated when an open circuit exists in said speed potentiometer.

Claim 4

A control in accordance with claim 1 wherein said means to reduce the duty cycle of said control pulses includes means for generating a narrow guard Pulse of the leading edge of each of said control pulses, and means responsive to each guard pulse to turn on said power switch and being responsive to said potentiometer failure signal in the absence of said guard pulse to terminate each said control pulse and thereby turn off said power switch.

Claim 5

A control in accordance with claim 3 wherein said means responsive to each said guard pulse to turn on said power switch includes logic gate means receiving said control pulses and being responsive to each said guard pulse to transmit said control pulse to said power switch and being responsive to said potentiometer failure signal in the absence of said guard pulse to block transmission of said control pulse.

Claim 6

In a variable time ratio control having a power switch regulated by variable duty cycle control pulses and means including a speed potentiometer for selectively varying the duty cycle of said control pulses, the improvement comprising means for detecting an open circuit in said speed potentiometer, and means controlled by said open potentiometer detecting means for reducing the duty cycle of said control pulses.

Claim 7

In a variable time ratio control having a power switch regulated by variable duty cycle control pulses and means including a speed potentiometer for selectively varying the duty cycle of said control pulses, the improvement comprising means for detecting an open circuit in said speed potentiometer, and means controlled by said open potentiometer detecting means for reducing the duty cycle of said control pulses.

Claim 8

In the combination of claim 5 wherein said means for selectively varying duty cycle includes control pulse transmitting means adapted when enabled and disabled respectively to transmit said control pulses to and to block said control pulses from said power switch, and wherein said means for reducing duty cycle includes means controlled by said open potentiometer detecting means for disabling said control pulse transmitting means.

Claim 9

In the combination of claim 6 wherein said open potentiometer detecting means includes a detecting transistor connected and arranged to be in a first operating state, means including a circuit completed through said speed potentiometer for biasing said detecting transistor to a second operating state, and means responsive to said detecting transistor being in said first and said second operating states respectively for disabling and enabling said control pulse transmitting means.

Claim 10

In combination with a variable time ratio control having a power switch regulated by variable duty cycle control pulses and means including a speed potentiometer for selectively varying the duty cycle of said control pulses; logic gate means adapted when enabled and disabled respectively to transmit said control pulses to and to block said control pulses from said power switch, an open potentiometer circuit detecting transistor connected and arranged to be in a first operating state, means including a circuit completed through said speed potonetiometer for biasing said open potentiometer detecting transistor to a second operating state, and means responsive to said open potentiometer detecting transistor being in said first and in said second operating states respectively for disabling and for enabling said logic gate means.

Claim 11

In combination with a variable time ratio control having a power switch regulated by variable duty cycle control pulses and means including a speed potentiometer for selectively varying the duty cycle of said control pulses; logic gate means adapted when enabled and disabled respectively to transmit said control pulses to and to block said control pulses from said power switch, an open potentiometer circuit detecting transistor connected and arranged to be in a first operating state, means including a circuit completed through said speed potonetiometer for biasing said open potentiometer detecting transistor to a second operating state, and means responsive to said open potentiometer detecting transistor being in said first and in said second operating states respectively for disabling and for enabling said logic gate means.

Claim 12

A control for supplying variable time ratio pulses from an electrical power source to a load comprising, in combination, a power switch between said source and said load turned on and off by control pulses applied thereto, an oscillator for providing a succession of triggering pulses, a monostable multivibrator triggered by each oscillator output pulse to generate a narrow guard pulse, variable delay means operated by each said triggering pulse to provide a timing signal after a time delay which is selectively adjustable by a speed potentiometer, potentiometer failure detection means for providing a potentiometer failure signal when the circuit through said speed potentiometer is open, bistable logic gate latch means triggered to a first condition by each guard pulse to generate a control signal to turn on said power switch and triggered to a second condition by said timing signal to turn off said power switch, and logic gate means between said latch means and said power switch adapted when enabled to transmit said control pulses to said power sWitch and being disabled by said potentiometer failure signal in the absence of a guard pulse and being enabled by each said guard pulse.

Claim 13

A control for supplying variable time ratio pulses from an electrical power source to a load comprising, in combination, a power switch between said source and said load turned on and off by control pulses applied thereto, an oscillator for providing a succession of triggering pulses, a monostable multivibrator triggered by each oscillator output pulse to generate a narrow guard pulse, variable delay means operated by each said triggering pulse to provide a timing signal after a time delay which is selectively adjustable by a speed potentiometer, potentiometer failure detection means for providing a potentiometer failure signal when the circuit through said speed potentiometer is open, bistable logic gate latch means triggered to a first condition by each guard pulse to generate a control signal to turn on said power switch and triggered to a second condition by said timing signal to turn off said power switch, and logic gate means between said latch means and said power switch adapted when enabled to transmit said control pulses to said power sWitch and being disabled by said potentiometer failure signal in the absence of a guard pulse and being enabled by each said guard pulse.

Claim 14

A control in accordance with claim 9 wherein said potentiometer failure detecting means includes transistor means for generating said potentiometer failure signal when said transistor means is turned off, and electrical circuit means completed through said speed potentiometer for biasing said transistor means to the conducting state.