Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
79 words
A signal processor for processing signals made up of more than one code, comprising: input means; means coupled to said input means for partly correlating the signals to correlate all but said one code; means for storing said partly correlated signals; and means coupled to said storage means for correlating said one code, including a shift register stitched in accordance with said one code selected stages of said shift register being coupled to predetermined portions of said storage means.
Claim 2
Dependent Claim
79 words
A signal processor for processing signals made up of more than one code, comprising: input means; means coupled to said input means for partly correlating the signals to correlate all but said one code; means for storing said partly correlated signals; and means coupled to said storage means for correlating said one code, including a shift register stitched in accordance with said one code selected stages of said shift register being coupled to predetermined portions of said storage means.
Claim 3
Dependent Claim
52 words
A signal processor as defined in claim 1, in which said correlation means further includes: a clock coupled to the input of said shift register; and a plurality of sense inversion switches, one coupled to each stage of said shift register, said sense inversion switches also being coupled to said storage means.
Claim 4
Dependent Claim
80 words
A signal processor as defined in claim 2, in which said means for storing said partly correlated signals includes: an orthogonal storage matrix comprising a multiplicity of bi-stable logic elements arranged in rows and columns, an electrical conductor connected to the bi-stable logic elements of each row of bi-stable logic elements, an electrical conductor connected to the bi-stable logic elements of each column of bi-stable logic elements; and means for applying said partly correlated signals to said orthogonal storage matrix.
Claim 5
Dependent Claim
74 words
A signal processor as defined in claim 3, in which said means for applying said partly correlated signals to said orthogonal storage matrix includes means for sequentially applying write pulses to the conductors connecting said columns of bi-stable logic elements simultaneously with the application of said partly correlated signals to the conductors connecting said rows of bi-stable logic elements, said write pulses being applied at the rate at which said one code was generated.
Claim 6
Dependent Claim
17 words
A signal processor as defined in claim 4, in which said bi-stable logic elements are magnetic cores.
Claim 7
Dependent Claim
103 words
In a pulse doppler radar system in which the transmitted signal is comprised of a first code modulated by at least one other code, each code representing different size range intervals, a receiver signal processor, comprising: input means; means coupled to said input means for partly correlating received target reflected signals to remove all but one code, thus acquiring fine range resolution in one broad ambiguous range interval; means for storing said partly correlated signals; means for correlating said one code in said stored signals; and a signal correlator coupled to said means for correlating said one code, said signal correlator resolving doppler.
Claim 8
Dependent Claim
103 words
In a pulse doppler radar system in which the transmitted signal is comprised of a first code modulated by at least one other code, each code representing different size range intervals, a receiver signal processor, comprising: input means; means coupled to said input means for partly correlating received target reflected signals to remove all but one code, thus acquiring fine range resolution in one broad ambiguous range interval; means for storing said partly correlated signals; means for correlating said one code in said stored signals; and a signal correlator coupled to said means for correlating said one code, said signal correlator resolving doppler.
Claim 9
Dependent Claim
53 words
A signal processor as defined in claim 6, in which said signal correlator includes at least one correlation network having a plurality of multi-level elements, each correlation network grouped to sum substantially all of a multiplicity of simultaneously presented pulses representing phase characteristics as a function of time of a particular signal only.
Claim 10
Dependent Claim
20 words
A signal processor as defined in claim 7, in which said multi-level elements are toroids having linear transformer magnetic characteristics.
Claim 11
Dependent Claim
74 words
A signal processor as defined in claim 6, in which said storing means includes: an orthogonal storage matrix comprising a multiplicity of bi-stable logic elements arranged in rows and columns, an electrical conductor connected to the bi-stable logic elements of each row of bi-stable logic elements, an electrical conductor connected to the bi-stable logic elements of each column of bi-stable logic elements; and means for applying said partly correlated signals to said orthogonal matrix.
Claim 12
Dependent Claim
36 words
A signal processor as defined in claim 9, in which said means for correlating said one code includes means coupling said storage means and said signal correlator for sense inverting selected bits of said stored signals.
Claim 13
Dependent Claim
45 words
A signal processor as defined in claim 10, in which said sense inverting means includes a plurality of sense inversion switches coupling the column electrical conductors of said storage matrix and said signal correlator and means for actuating selected ones of said sense inversion switches.
Claim 14
Dependent Claim
27 words
A signal processor as defined in claim 11, further including a plurality of memory devices, one coupling each row electrical conductor to its respective sense inversion switch.
Claim 15
Dependent Claim
25 words
A signal processor as defined in claim 11, in which said means for actuating selected one of said sense inversion switches includes a shift register.
Claim 16
Dependent Claim
21 words
A signal processor as defined in claim 13, in which said shift register is wired in accordance with said one code.
Claim 17
Dependent Claim
20 words
A signal processor as defined in claim 14, further including means for advancing said one code through said shift register.
Claim 18
Independent Claim
66 words
A method for resolving range and doppler of received target signals after transmitting a signal comprising a first code modulated by one or more codes, comprising the steps of: compressing the received signals to remove all but one code; storing the partly correlated signals; altering the stored signals to remove said one code; and summing the resultant signals in accordance with predetermined programs representing various dopplers.
Claim 19
Independent Claim
66 words
A method for resolving range and doppler of received target signals after transmitting a signal comprising a first code modulated by one or more codes, comprising the steps of: compressing the received signals to remove all but one code; storing the partly correlated signals; altering the stored signals to remove said one code; and summing the resultant signals in accordance with predetermined programs representing various dopplers.