Abstract A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.
An integrated semiconductor memory cell structure comprising: a semiconductor member of one type conductivity: first and second spaced opposing common emitter regions of opposite type conductivity disposed in the vertical direction, said emitter regions extending from one planar surface of said member into said member; first and second spaced opposing common emitter regions of said opposite type conductivity disposed in the horizontal direction intermediate said vertically disposed common emitters, said horizontally disposed emitter regions also extending from one plenar surface of said member into said member; at least first and second discrete base regions of said one type conductivity extending from said planar surface and enclosed within each emitter region; a collector region of said opposite type conductivity extending from said planar surface and enclosed within each base region; an electrically insulating layer covering said surface; ohmic contacts to at least all of said base and emitter regions extending through said insulative layer; and metallic interconnectors formed on said insulating layer connecting: each of the base regions in the vertically disposed emitters to a base region in the horizontally disposed emitters. the collector regions of each connected base pair to each other, by cross-coupling, the collectors and bases of the first horizontally disposed emitter, and by cross-coupling, the collectors and bases of the second horizontally disposed emitter.
Claim 2
Dependent Claim
217 words
An integrated semiconductor memory cell structure comprising: a semiconductor member of one type conductivity: first and second spaced opposing common emitter regions of opposite type conductivity disposed in the vertical direction, said emitter regions extending from one planar surface of said member into said member; first and second spaced opposing common emitter regions of said opposite type conductivity disposed in the horizontal direction intermediate said vertically disposed common emitters, said horizontally disposed emitter regions also extending from one plenar surface of said member into said member; at least first and second discrete base regions of said one type conductivity extending from said planar surface and enclosed within each emitter region; a collector region of said opposite type conductivity extending from said planar surface and enclosed within each base region; an electrically insulating layer covering said surface; ohmic contacts to at least all of said base and emitter regions extending through said insulative layer; and metallic interconnectors formed on said insulating layer connecting: each of the base regions in the vertically disposed emitters to a base region in the horizontally disposed emitters. the collector regions of each connected base pair to each other, by cross-coupling, the collectors and bases of the first horizontally disposed emitter, and by cross-coupling, the collectors and bases of the second horizontally disposed emitter.
Claim 3
Dependent Claim
22 words
The integrated memory cell structure of claim 1 wherein the emitter regions have a higher majority carrier concentration than said base regions.
Claim 4
Dependent Claim
113 words
The structure of claim 1 wherein said semiconductor member is a composite of a semiconductor substrate of one type conductivity and an epitaxial semiconductor layer of said one type conductivity; each of said common emitters is formed by the combination of a buried region of opposite type conductivity located in the substrate at the interface with the epitaxial layer and a circumscribing region of said opposite type conductivity extending from the outer surface of said epitaxial layer to contact the buried region to fully enclose a pair of discrete portions of the epitaxial layer; and the pAir of enclosed discrete portions form the first and second base regions within the common emitter region.