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US3800239A Expired / Lapsed US ⏱️ 0.0 years remaining

Current-canceling circuit

Assignee: Texas Instruments Inc
•
Filing: 1972-11-24
•
Granted: 1974-03-26
•
Expires: 1992-11-24
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Abstract

Abstract A current-canceling circuit coupled to the input of a differential amplifier stage nulls normal input currents resulting from base bias and leakage currents. Hfe match of only one pair of devices per input is required by utilizing a split collector transistor as a current source to supply compensation current to the input transistor.

Inventors

  • 👤 M Callahan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 12:51
CPC Classifications
H; H03; H03J; H03J5/00; H03J5/24; H03J5/242; H03J5/244; H03B; H03B5/00; H03B5/08; H03B5/12; H03B5/1203; H03B5/1231; H03B5/1237; H03B5/124; H03B5/1243; H03F; H03F1/00; H03F1/56; H03F3/00; H03F3/45; H03F3/45071; H03B2200/00; H03B2200/003; H03B2200/004; H03B2200/0048; H03B2200/0056; H03B2201/00; H03B2201/02; H03B2201/0208

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 220 words
In a differential stage electrical amplifier having a pair of npn input transistor for receiving first and second input signals at the respective base electrodes thereof, a current canceling circuit coupled to one of said input transistors comprising: a. a third npn transistor having its emitter coupled to the collector of one of said pair of input transistors, b. a first pnp transistor having its base commonly connected to the base of third npn transistor and having its collector coupled to a first energization source, c. a second pnp transistor having a plurality of collectors, one of said collectors connected to the base of said third npn transistor, and having its base connected to the emitter of said first pnp transistor, and having its emitter connected to a second energization source, d. a first set of serially connected diodes connecting said second energization source to the collector of said third npn transistor, e. a second set of serially connected diodes serially connected between said first set of diodes and the emitter of said one input transistor, and f. at least another diode connecting the other of said plurality of collectors of said second pnp transistor to the base of said one input transistor, thereby providing a biased differential stage having a compensated input for canceling input current to the stage.
Claim 2
Dependent Claim 220 words
In a differential stage electrical amplifier having a pair of npn input transistor for receiving first and second input signals at the respective base electrodes thereof, a current canceling circuit coupled to one of said input transistors comprising: a. a third npn transistor having its emitter coupled to the collector of one of said pair of input transistors, b. a first pnp transistor having its base commonly connected to the base of third npn transistor and having its collector coupled to a first energization source, c. a second pnp transistor having a plurality of collectors, one of said collectors connected to the base of said third npn transistor, and having its base connected to the emitter of said first pnp transistor, and having its emitter connected to a second energization source, d. a first set of serially connected diodes connecting said second energization source to the collector of said third npn transistor, e. a second set of serially connected diodes serially connected between said first set of diodes and the emitter of said one input transistor, and f. at least another diode connecting the other of said plurality of collectors of said second pnp transistor to the base of said one input transistor, thereby providing a biased differential stage having a compensated input for canceling input current to the stage.
Claim 3
Dependent Claim 20 words
The differential stage according to claim 1 wherein said first and second sets of diodes each consists of two diodes.
Claim 4
Dependent Claim 33 words
The differential stage according to claim 2 wherein said second pnp transistor consists of a multi-collector lateral pnp transistor integrated in combination with said other transistors and diodes in a single semiconductor chip.

References Cited (Backward Citations)

US3714600A Cited
US3614645A Cited
US3538449A Cited
US3633052A Cited
US3629691A Cited
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US3700921A Cited
US3717821A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-03-25 1977-09-24 1978-03-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-03-25 1981-09-24 1982-03-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-03-25 1985-09-24 1986-03-26 $7700.00 Window Closed / Lapsed

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