High voltage solid state switching techniques

Claim 2

A control circuit for a transistor connected to a substantially capacitive load, such transistor having an emitter, a collector and a base, comprising: first means including timing means for providing a hard drive bias current to said base for a predetermined time while charging said capacitive load and for providing an idle drive bias current to said base after said predetermined time, second means independent of said first means for controlling said first means, and third means independent of said first and said second means for providing a positively acting off bias voltage to said base.

Claim 3

The control circuit according to claim 1 wherein said timing means comprises an RC circuit.

Claim 4

The control circuit according to claim 1 wherein said first means includes a capacitor maintainable in a predetermined state of charge and a low impedance connection from said capacitor to said base.

Claim 5

In an on-off switching circuit for a plurality of series connected switching transistors connecting an essentially capacitive load to a voltage source having a voltage higher than the blocking voltage of each of said plurality of switching transistors, each of said switching transistors having an emitter, a collector, and a base, control means for said plurality of switching transistors comprising: first means including timing means individual to each of said switching transistors for simultaneously providing a hard drive bias current to the base of each of said transistors for a predetermined time after a turn-on signal, while charging said capacitive load and for simultaneously providing an idle drive bias current to the base electrode of each of said switching transistors after said predetermined time, second means individual to each of said switching transistors and independent of said first means for controlling said first means, and third means individual to each of said switching transistors and independent of said first and said second means for simultaneously providing after a signal therEfor a positively acting off bias voltage to the base of each of said switching transistors.

Claim 6

In an on-off switching circuit for a plurality of series connected switching transistors connecting an essentially capacitive load to a voltage source having a voltage higher than the blocking voltage of each of said plurality of switching transistors, each of said switching transistors having an emitter, a collector, and a base, control means for said plurality of switching transistors comprising: first means including timing means individual to each of said switching transistors for simultaneously providing a hard drive bias current to the base of each of said transistors for a predetermined time after a turn-on signal, while charging said capacitive load and for simultaneously providing an idle drive bias current to the base electrode of each of said switching transistors after said predetermined time, second means individual to each of said switching transistors and independent of said first means for controlling said first means, and third means individual to each of said switching transistors and independent of said first and said second means for simultaneously providing after a signal therEfor a positively acting off bias voltage to the base of each of said switching transistors.

Claim 7

The control circuit according to claim 4 wherein said timing means comprises an RC circuit.

Claim 8

The control circuit according to claim 4 wherein said first means comprises, for each switching transistor, a capacitor maintainable in a predetermined state of charge, a first source of current for charging said capacitor, a low impedance circuit between said capacitor and the base of the switching transistor, and a relatively high impedance circuit between said first source of current and the base of the switching transistor.

Claim 9

The control circuit according to claim 6 wherein said low impedance circuit comprises a second transistor whose emitter-collector circuit is connected between the capacitor and the base of the switching transistor, the base of said second transistor receiving said turn-on signal and being responsive to said timing means.

Claim 10

The control circuit according to claim 7 wherein the timing means comprises an RC circuit. 9 . The control circuit according to claim 6 wherein said relatively high impedance circuit comprises a third transistor whose emitter-collector circuit is connected between one terminal of said source of current and the base of said switching transistor and whose base receives said turn-on signal, and a relatively high impedance means connected in the emitter-collector circuit of said third transistor.

Claim 11

The control circuit according to claim 9 wherein said high impedance means comprises a resistance means.

Claim 12

The control circuit according to claim 9 wherein said second means comprises for each of said switching transistors a second source of current and circuit means connecting said second source of current to the bases of said second and said third transistors.

Claim 13

The control circuit according to claim 4 wherein said first means comprises for each switching transistor, a capacitor maintainable in a predetermined state of charge, a first source of current for charging said capacitor, a second transistor whose emitter-collector circuit is connected in a low impedance circuit between said capacitor and the base of said switching transistor, and a third transistor whose emitter-collector circuit is connected in a relatively high impedance circuit between one terminal of said first source of current and the base of said switching transistor; and said second means comprises for each of said switching transistors respectively, a second source of current, the base of said second transistor being connected to said second source of current for providing a turn-on signal for said second transistor, timing means connected to the base of said second transistor, the base of said third transistor being connected to said second source of current for providing a turn-on signal for said third transistor, and a relatively high impedance connected in the emitter-collector circuit of said third transistor.

Claim 14

The control circuit according to claim 12 wherein said timing circuit comprises an RC circuit having a predetermined time constant.

Claim 15

The control circuit according to claim 12 wherein the third means individual to each of said switching transistors and independent of said first and said second means for simultaneously providing, after a signal therefor, an ''''off'''' voltage to the base of each said switching transistors comprises, for each of said switching transistors, respectively, a third source of current, and a fourth transistor whose emitter-collector circuit is connected in a relatively low impedance circuit with the base of said switching transistor and one terminal of said third source of current, and whose base is connected to the other terminal of said third source of current.

Claim 16

The control circuit according to claim 14 wherein the circuit of the capacitor of said first means includes means for limiting the charge accumulatable thereon.

Claim 17

The control circuit according to claim 15 wherein said charge limiting means comprises a fifth transistor whose emitter-collector circuit is connected in a relatively high impedance circuit with said capacitor and whose base is connected to one terminal of said capacitor for supplying a control voltage.

Claim 18

The control circuit according to claim 16 wherein the relatively high impedance on the emitter-collector circuit of said fifth transistor is essentially the same as that of said third transistor.

Claim 19

The control circuit according to claim 4 wherein, for each switching transistor, the first means, second means and third means include separate transformers each having a primary winding and at least one secondary winding and the first, second and third current sources each include rectifier means connected, respectively, to the secondary windings of said transformers.

Claim 20

A transistor switch structure comprising: a plurality of series connected switching transistors for connecting a substantially capacitive load to a current source whose voltage exceeds the blocking voltage of each of said plurality of switching transistors, each of said switching transistors having an emitter, a collector, and a base; first means including timing means individual to each of said switching transistors for simultaneously providing a hard drive bias current to the base electrode of each of said switching transistors for a predetermined time after a turn-on signal, while charging said capacitive load and an idle drive bias current to the base electrode of each of said switching transistors after said predetermined time; second means individual to each of said switching transistors and independent of said first means for controlling said first means; and third means individual to each of said switching transistors and independent of said first and said second means for simultaneously providing, after a signal therefor, a positively acting off bias voltage to the base of each of said switching transistors.

Claim 21

A transistor switch structure comprising: a plurality of series connected switching transistors for connecting a substantially capacitive load to a current source whose voltage exceeds the blocking voltage of each of said plurality of switching transistors, each of said switching transistors having an emitter, a collector, and a base; first means including timing means individual to each of said switching transistors for simultaneously providing a hard drive bias current to the base electrode of each of said switching transistors for a predetermined time after a turn-on signal, while charging said capacitive load and an idle drive bias current to the base electrode of each of said switching transistors after said predetermined time; second means individual to each of said switching transistors and independent of said first means for controlling said first means; and third means individual to each of said switching transistors and independent of said first and said second means for simultaneously providing, after a signal therefor, a positively acting off bias voltage to the base of each of said switching transistors.

Claim 22

The transistor switch structure according to claim 19 wherein: said first means comprises, for each switching transistor, a capacitor maintainable in a predetermined state of charge, a first source of current for charging said capacitor, a second transistor whose emitter-collector circuit is connected between the capacitor and the base of the switching transistor, the base of said second transistor receiving said turn-on signal and being responsive to said timing means, a third transistor whose emitter-collector circuit is connected between one terminal of said first source of current and the base of said switching transistor, the base of said third transistor being connected to the other terminal of said first source of current, and a relatively high resistance means connected in the emitter-collector circuit of said third transistor; said second means comprises for each of said switching transistors respectively, a second source of current, the base of said second transistor being connected to said second source of current for providing a turn-on signal for said second transistor, timing means connected to the base of said first transistor; the base of said third transistor being connected to said second source of current for providing a turn-on signal for said third transistor, and a relatively high impedance connected in the emitter-collector circuit of said third transistor, and said third means comprises, for each of said switching transistors, respectively, a third source of current, and a fourth transistor whose emitter-collector circuit is connected in a relatively low impedance circuit with the base of said switching transistor and one terminal of said third source of current, and whose base is connected to the other terminal of said third source of current.

Claim 23

A switching circuit for connecting and disconnecting one or more of more than one voltAge sources to an essentially capacitive load comprising: a series of transistor switch sections, the switching transistors of which have a blocking voltage less than the voltage of one of said current sources; first control means for selecting a predetermined number of switch sections of said series and closing the same to effect connecting the correlated number of said voltage sources through said switch sections to said load, and further control means cooperating with said first control means for opening the remaining ones of said switch sections prior to said closing.

Claim 24

A switching circuit for connecting and disconnecting one or more of more than one voltAge sources to an essentially capacitive load comprising: a series of transistor switch sections, the switching transistors of which have a blocking voltage less than the voltage of one of said current sources; first control means for selecting a predetermined number of switch sections of said series and closing the same to effect connecting the correlated number of said voltage sources through said switch sections to said load, and further control means cooperating with said first control means for opening the remaining ones of said switch sections prior to said closing.

Claim 25

The switching circuit according to claim 21 wherein each one of said series of switch sections comprises: a plurality of series connected switching transistors for connecting an essentially capacitive load to a current source whose voltage exceeds the blocking voltage of each of said plurality of switching transistors, each of said switching transistors having an emitter, a collector, and a base, first means including timing means individual to each of said switching transistors for simultaneously providing a hard drive bias current to the base electrode of each of said transistors for a predetermined time after a turn-on signal, while charging said capacitive load and for simultaneously providing an idle drive bias current to the base electrode of each of said switching transistors after said predetermined time, second means individual to each of said switching transistors and independent of said first means for controlling said first means, and third means individual to each of said switching transistors and independent of said first and said second means for simultaneously providing after a signal therefor a positively acting off bias voltage to the base of each of said switching transistors.

Claim 26

The switching circuit according to claim 22 wherein each one of said series of switch sections comprises: a capacitor maintainable in a predetermined state of charge, a first source of current for charging said capacitor, a second transistor whose emitter-collector circuit is connected between the capacitor and the base of the switching transistor, the base of said second transistor receiving said turn-on signal and being responsive to said timing means, a third transistor whose emitter-collector circuit is connected between one terminal of said first source of current and the base of said switching transistor, the base of said third transistor being adapted to receive said turn-on signal, and high resistance means connected in the emitter-collector circuit of said third transistor; said second means comprises, for each of said switching transistors respectively, a second source of current; the base of said second transistor being connected to said second source of current for providing said turn-on signal for said second transistor; said timing means being connected to the base of said second transistor; the base of said third transistor being connected to said second source of current for providing said turn-on signal and a relatively high impedance connected in the emitter-collector circuit of said third transistor; and said third means comprises, for each of said switching transistors respectively: a third source of current, and a fourth transistor whose emitter-collector circuit is connected in a relatively low impedance circuit with the base of said switching transistor and one terminal of said third source of current, the base of said fourth transistor being adapted to be connected to the other terminal of said third source of current.

Claim 27

The switching structure according to claim 19 wherein for each switching transistor the first means, second means and third means include separate transformers each having a primary winding and at least one secondary winding and the first, second and third current sources each include a rectifier connected, respectively, to the secondary windings of said transformerS.