Remote coded dual state controller apparatus

Claim 2

In an automated communication system wherein a message frame is circulated through a communication loop for selective coupling to any one of a plurality of remote stations having frame handling means and point modules, at least one of said stations having a point module for controlling a multiple load means, the improvement wherein said point module includes an address decoding means coupled through a common bus means to said frame handling means and having a comparator producing an output signal in response to a selected comparison of the incoming message frame with a selected coded address, a latch means connected to the decoding means and establishing a latched point module enable signal in response to the output of said comparator, a command latch and decoding means connected to said common bus means and connected to the latch means and set to establish one of a plurality of operational output means, selection means connected by said common bus means to said frame handling means and operative to enable selectively corresponding load means of said point module, and a power isolating circuit means connected to said load means and conjointly responsive to the signal of the point selection means and command latch and decoding means and operable to establish the selected operating state.

Claim 3

The automated communication system of claim 1 wherein said address decoding means includes a point module address available signal line responsive to a signal on common bus means to control establishing of said latch means, said command latch and decoding means including a command available signal means responsive to the outPut of said latch means and a common available signal on the common bus means, and said load means selection means including a selection available signal means responsive to the output of said latch means and said command latch and decoding means and a selection available signal on the common bus means to activate a pulse circuit means for generating the power isolating circuit means.

Claim 4

In the automated communication system of claim 1 wherein said message frame includes a plurality of binary coded bits circulated through the communication loop wherein said address decoding circuit includes a point module available signal line coupled to said frame handling circuit indicating proper insertion of the address data, said command latch and decoding means includes a plurality of registers coupled through said common bus lines to said frame handling means and receiving a binary code related to any one of a plurality of fixed operations, said registers having an activating input means connected and responsive conjointly to said point module enable signal and a command enable signal generated by the frame handling means indicating proper insertion of the command data code to said registers, a decoding means connected in common to the output of said registers and selectively establishing outputs related respectively to the first and second operating status of the load means, an initiate signal means interconnected to the output of said registers to produce a common interlock signal, and means connecting said point enable signal and said interlock signal to conjointly control said power isolating circuit means.

Claim 5

The communication system of claim 1 wherein said isolation means includes a plurality of individual binary input means connected respectively via common bus lines to said frame handling means, each of said lines being related to a particular equipment means and each of said lines receiving a binary signal in accordance with the selection or non-selection of the corresponding equipment, coupling circuit means connected between said input means and output selection lines connected respectively to said several load means, interlocking logic control means responsive to the address decoding means and command latch and decoding means and the input means of the selection means for simultaneously transferring the signal on the input means to the coupling circuit means and operating said pulse circuit means.

Claim 6

The communication system of claim 1 wherein said isolating circuit means includes individual relay means connected for alternately establishing either of two states of operation of the load means, each of said relay means including a combining circuit conjointly responsive to the signal of the selection means and of the pulse circuit means and operable to provide a timed relay energization to actuate a set of isolating control contacts connected to a load means control.

Claim 7

The communication system of claim 5 having means for monitoring the operational status of the load means, wherein a condition sensing relay includes a winding connected in series with said status contacts and having a set of low current status contacts, said status contacts being connected to a low voltage logic supply in series with a voltage dropping resistor, the connection of the resistor and the contact sensing contacts providing a logic signal, said command latch and decoding means including a read output means, means to store said logic signal and selectively transfer said signal to said common bus lines for loop communication in response to said read output means.

Claim 8

The automated communication system of claim 1 having means for monitoring the operational status of the load means, wherein said power isolating circuit means includes a separate power contact connecting the load to an operational power source, condition sensing means connected in circuit with said power contacts and having separate status indicating means, said status means providing a logic signal, said command latch and decodiNg means including a read output means, means to store said logic signal and selectively transfer said signal to said common bus lines for loop communication in response to said read output means.

Claim 9

The automated communication system of claim 1 wherein said command latch and decoding means including a plurality of registers coupled through common bus lines of said bus means to said frame handling means and receiving a binary code related to any one of a plurality of fixed operations including a first state establishing operation, a second state establishing oeration and a status read operation, said registers having an activating input means connected responsive conjointly to said address decoding means and a command enable signal generated by the frame handling means indicating proper insertion of the command data code to said registers, a decoding means connected in common to the output of said registers and selectively establishing one of three outputs related respectively to the first establishing state, the second state establishing state and a third read state.

Claim 10

The automated communication system of claim 8 including a common read or initiate logic means interconnected to the output of each of said registers and the read state output means of the command means to produce a common interlock signal for operation of the selection means.

Claim 11

In the system of claim 1, wherein the address decoding circuit includes a plurality of switch means selectively interconnecting and a multiple input binary comparator having a pair of inputs for each address position, one of said pair of inputs being connected by a single pole by a switch means to positive logic signal source or to logic ground, the other of said comparator inputs for each position being connected to a common bus line to receive the corresponding binary logic signal, said comparator comparing the multiple input address and establishing an output signal upon identical inputs at each address pair, a flip-flop circuit having a first input connected to the output of the comparator and having a clock input connected to the common bus line for receiving the point module address available signal for selective setting of said register and establishing of said output signal for enabling of the point module for intercommunication or receipt and transmission with respect to the message frame, said register having a clear terminal input means connected to a common bus line and reset in response only to a specific command signal transmitted by the frame handling means to said reset common bus lines.

Claim 12

In an automated communication system wherein a multiple bit control message frame is circulated through a communication loop for selective coupling to any one of a plurality of remote stations having a message frame handling means and point modules, at least one of said stations having one point module for controlling a plurality of load means in combination with means for monitoring the status of at least selected load means each remote station having a common bus cable connecting the point modules in common to said frame handling means, the improvement wherein said one point module includes a multiple bit address decoding circuit including a binary decoder comparator including a plurality of set inputs defining a unique point address and a plurality of frame inputs coupled through a plurality of common bus lines to said frame handling means, a latch circuit connected to the output of said comparator for establishing a latched point module enable signal line in response to the output of said comparator said address decoding circuit including a point module available signal line coupled to said frame handling means to activate said latch circuit in response to a signal from the frame handling means indicating proper insertion of the address data on said comparator means, a command latch and decoding circuit including a plurality of second latch circuits coupled through said common bus lines to said frame handling means and rEceiving a binary code related to any one of a plurality of fixed operations including a first state establishing operation, a second state establishing operation and a status read operation, said second latch circuits having an activating input means connected and responsive conjointly to said point module enable signal line and a command enable signal generated by the frame handling means indicating proper insertion of the command data code to said latch circuits, a decoding means connected in common to the output of said second latch circuits and selectively establishing one of three output means related respectively to the first establishing state and the second state establishing state and the third read state, a common read or initiate signal means interconnected to the output of each of said second latch circuits and the read state output means to produce a common interlock signal, said point modules further including a load selection means having a plurality of individual binary selection input means connected respectively via common bus lines to said frame handling means, each of said lines being related to a particular load means and each of said lines receiving a binary selection signal in accordance with the selection or non-selection of the corresponding equipment and connected to enable a corresponding load means for operation, interlocking control means including first logic means for combining the point module enable signal, the common command signal of the command latch and decoding circuit and a data available signal generated by the frame handling means and creating first and second operational signals to actuate the load means conjointly with the binary selection signals to place the load means in the selected operational state.

Claim 13

In an automated communication system wherein a multiple bit control message frame is circulated through a communication loop for selective coupling to any one of a plurality of remote stations having a message frame handling means and point modules, at least one of said stations having one point module for controlling a plurality of load means in combination with means for monitoring the status of at least selected load means each remote station having a common bus cable connecting the point modules in common to said frame handling means, the improvement wherein said one point module includes a multiple bit address decoding circuit including a binary decoder comparator including a plurality of set inputs defining a unique point address and a plurality of frame inputs coupled through a plurality of common bus lines to said frame handling means, a latch circuit connected to the output of said comparator for establishing a latched point module enable signal line in response to the output of said comparator said address decoding circuit including a point module available signal line coupled to said frame handling means to activate said latch circuit in response to a signal from the frame handling means indicating proper insertion of the address data on said comparator means, a command latch and decoding circuit including a plurality of second latch circuits coupled through said common bus lines to said frame handling means and rEceiving a binary code related to any one of a plurality of fixed operations including a first state establishing operation, a second state establishing operation and a status read operation, said second latch circuits having an activating input means connected and responsive conjointly to said point module enable signal line and a command enable signal generated by the frame handling means indicating proper insertion of the command data code to said latch circuits, a decoding means connected in common to the output of said second latch circuits and selectively establishing one of three output means related respectively to the first establishing state and the second state establishing state and the third read state, a common read or initiate signal means interconnected to the output of each of said second latch circuits and the read state output means to produce a common interlock signal, said point modules further including a load selection means having a plurality of individual binary selection input means connected respectively via common bus lines to said frame handling means, each of said lines being related to a particular load means and each of said lines receiving a binary selection signal in accordance with the selection or non-selection of the corresponding equipment and connected to enable a corresponding load means for operation, interlocking control means including first logic means for combining the point module enable signal, the common command signal of the command latch and decoding circuit and a data available signal generated by the frame handling means and creating first and second operational signals to actuate the load means conjointly with the binary selection signals to place the load means in the selected operational state.

Claim 14

The communication system of claim 11 having a power isolating relay circuit connected between said control means and the load means and having individual relay means connected for alternately establishing said two states, each of said relay means including a combining circuit conjointly responsive to the operational signals and the selection signal and operable to provide timed energization of a corresponding relay winding to actuate a set of separate isolating control contacts connected to the load means.

Claim 15

The communication system of claim 12 having a status sensing relay means including a winding connected in series with said control contacts and having a set of status contacts, said status contacts being connected to a low voltage logic supply in series with a voltage dropping resistor, the connection of the resistor and the contact sensing contacts providing a logic signal, means to store said logic signal and responsive to the read state output of said command latch and decoding circuit to transfer said signal to said common bus lines for loop communication.

Claim 16

In the system of claim 11 wherein the point module address decoding circuit includes a plurality of switch means selectively interconnecting and a multiple input binary comparator having a pair of inputs for each address position, one of said pair of inputs being connected by a switch means to a positive logic signal source or to logic ground, the other of said comparator inputs for each position being connected to a different common bus line to receive the corresponding binary logic signal, said comparator comparing the multiple input address and establishing an output signal upon identical inputs at each address pair, a latch circuit having a first input connected to the output of the comparator and having a clock input connected to the common bus line for receiving the point module address available signal for selective setting of said latch circuit and establishing of said enable signal for enabling of the point module for intercommunication or receipt and transmission with respect to the message frame, said latch circuit having a clear terminal input means connected to a common bus line and reset in response only to a specific command signal transMitted by the frame handling means to said reset common bus line.

Claim 17

In the communication system of claim 11 wherein the command latch and decoding circuit includes a plurality of individual binary signal registers each having a corresponding input connected to a selected common bus line, each of said registers having a clock input means, a logic gate having an output connected to said clock terminals in common and having a first input connected to the point module enable signal line and a second input connected to a common bus line for receipt of the command available signal from the frame handling means, said registers each having a clear signal input means connected in common to a common reset bus line, a multiple input decoder having each of the inputs connected to the output of a corresponding register and having individual outputs including one for each of said three outputs, and a logic circuit means connected to the outputs of all registers and to the read output of the multiple input decoder and providing a common interlock signal output for selectively and conjointly with said individual outputs enabling the point selection means and load means.

Claim 18

The communication system of claim 15 wherein said logic circuits means includes a first logic gate connected to the output of the registers to establish an output in response to an output from anyone of such registers, and a second logic gate connected to the first logic gate and the read output to create a read or initiate interlock output.

Claim 19

In the communication system of claim 11 wherein the selection means includes a clocked coupling circuit having an individual input for each load means for receiving the corresponding binary signal from the frame handling means, said coupling means having a clock input, a combining logic gate means having three inputs connected respectively to a bus line for receiving a data available signal from said frame handling means and a second input connected to the point module latch circuit to receive the enable signal and a third input connected to the command means and establishing an output signal in response to simultaneous receipt of the corresponding inputs, said logic gate means being connected to actuate said coupling circuit to transmit the information to load lines, and timed means to actuate the load means in accordance with the output of the logic gate means and the output of the command latch and decoding circuit.

Claim 20

The communication system of claim 17 wherein said timed means includes a timing means connected to the output of the logic gate means and establishing a precise timed pulse, second logic means connected to the timing means and the command circuit means and providing a pair of related timed output signals, a pair of output logic gate means having connected one each to the second logic means and in common to the output of the road lines.

Claim 21

In the communication system of claim 11 wherein the selection means includes a clocked coupling circuit having an individual input for each load means for receiving the corresponding binary signal from the frame handling means, said coupling means having a clock input, a combining logic gate means having three inputs connected respectively to a bus line for receiving a data available signal from said frame handling means and a second input connected to the point module latch circuit to receive the enable signal and a third input connected to the command means and establishing an output signal in response to simultaneous receipt of the corresponding inputs, said logic gate means being connected to actuate said coupling circuit to transmit the information to load lines, a solid state amplifier having a timing means connected to the output of the logic gate means and establishing a precise timed pulse, a flip-flop means having a pair of inputs connected to the operation command signal means of the decoding circuit of the command circuit means and providing related output signals, a pair of logic gate means having a firSt input connected in common to the output of the amplifier and having the second inputs connected respectively to the outputs of the command flip-flop, a pair of relay units for each load means having a pair of two input NAND logic gates, the first input of both NAND gates being connected in common to the corresponding load line from the coupling circuit and the second input being connected respectively to the logic gate means providing pulsed input signals in accordance with the pulse signal from the amplifier, each of said relay units having a winding connected by the NAND gate to a logic supply and a set of normally open contacts connected from an isolated operating voltage to an isolated common line, pulsed operation of such normally open contacts being operable to actuate said load means.

Claim 22

The communication system of claim 19 having a contact sensing relay including a winding connected in series with motor status contacts and a set of sensing contacts, a logic power supply, a sensing means connected to the logic power supply in series with said sensing contacts, and a contact sensing register means connected to said sensing means to record the operation of the motor and maintain a contact status output signal in said register.