US3796956A
Expired / Lapsed
US
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Block synchronization system of multinary codes
Assignee: Fujitsu Ltd
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Filing: 1971-12-20
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Granted: 1974-03-12
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Expires: 1991-12-20
Abstract
Abstract A multinary transmission system transmits multinary code blocks converted in block unit from binary codes. When two identical code blocks are to be transmitted continuously, the succeeding code block is converted into a code block having special patterns so that the same pattern as the patterns of the preceding code block may not appear in the succeeding code block. Thus, the multinary code block is so constituted that no specific two codes may be generated continuously and transmission is such that the specific two codes may be continuous only at the break point of the block. Block synchronization is provided at the receiver by detecting the special patterns or by detecting two specific continuous codes.
Inventors
- 👤 I Fudemoto
- 👤 M Sakai
- 👤 Y Fujisaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:49
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4919
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
384 words
A block synchronization system of multinary codes in a multinary transmission system which transmits multinary code blocks converted in a block unit from binary PCM signals, said block synchronization system comprising transmitting means having input means supplying binary PCM signals, regular converting circuit means having an input connected to the input means for converting the binary PCM signals into code blocks each having four multinary code digits and having output means, pattern discriminating circuit means having an input connected to the output means of the regular converting circuit means for checking checking algebraic sum of the four multinary code digits in each code block and providing an output signal when the albebraic sum is negative and having an output, and having means for comparing successive patterns of the code blocks irregular converting circuit means having an input connected to the output means of the regular converting circuit means for converting the code block of the regular converting circuit means into a code block having no two specific codes continuously one after the other when the sum of the four multinary code digits in the code block of the regular converting circuit means is negative and having an output, synchronized pattern generating circuit means having an input connected to the output of the pattern discriminating circuit means for generating a code block having a pattern different from the patterns of the code blocks of the regular converting circuit means and the irregular converting circuit means when the pattern discriminating circuit means further detects the same patterns of the code blocks of the regular converting circuit means continuously and having an output, and transmitter output means connected to the output means of the regular converting circuit means and connected to the outputs of the pattern discriminating circuit means, the irregular converting circuit means and the synchronized pattern generating circuit means for transmitting the code block of the irregular converting circuit means when the pattern discriminating circuit means provides the output signal and the code block of the synchronized pattern generating circuit means when the pattern discriminating circuit means further detects the same patterns of the code blocks of the regular converting circuit means continuously; and receiving means for receiving the transmitted code blocks having detecting means for detecting two specific codes continuously and providing block synchronization.
Claim 2
Dependent Claim
384 words
A block synchronization system of multinary codes in a multinary transmission system which transmits multinary code blocks converted in a block unit from binary PCM signals, said block synchronization system comprising transmitting means having input means supplying binary PCM signals, regular converting circuit means having an input connected to the input means for converting the binary PCM signals into code blocks each having four multinary code digits and having output means, pattern discriminating circuit means having an input connected to the output means of the regular converting circuit means for checking checking algebraic sum of the four multinary code digits in each code block and providing an output signal when the albebraic sum is negative and having an output, and having means for comparing successive patterns of the code blocks irregular converting circuit means having an input connected to the output means of the regular converting circuit means for converting the code block of the regular converting circuit means into a code block having no two specific codes continuously one after the other when the sum of the four multinary code digits in the code block of the regular converting circuit means is negative and having an output, synchronized pattern generating circuit means having an input connected to the output of the pattern discriminating circuit means for generating a code block having a pattern different from the patterns of the code blocks of the regular converting circuit means and the irregular converting circuit means when the pattern discriminating circuit means further detects the same patterns of the code blocks of the regular converting circuit means continuously and having an output, and transmitter output means connected to the output means of the regular converting circuit means and connected to the outputs of the pattern discriminating circuit means, the irregular converting circuit means and the synchronized pattern generating circuit means for transmitting the code block of the irregular converting circuit means when the pattern discriminating circuit means provides the output signal and the code block of the synchronized pattern generating circuit means when the pattern discriminating circuit means further detects the same patterns of the code blocks of the regular converting circuit means continuously; and receiving means for receiving the transmitted code blocks having detecting means for detecting two specific codes continuously and providing block synchronization.
Claim 3
Dependent Claim
17 words
A block synchronization system as claimed in claim 1, wherein the multinary code is a quaternary code.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-11 | 1977-09-10 | 1978-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-11 | 1981-09-10 | 1982-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-11 | 1985-09-10 | 1986-03-12 | $7700.00 | Window Closed / Lapsed |