Telephone line seizure switches

Claim 2

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears, which may have an associated telephone set and for actuating associated apparatus, comprising a capacitor, a semiconductor having a control element and two current conducting terminals, a power source, said capacitor, said control element and one of said current conducting terminals connected in series reactively across said telephone line, time delay means producing a triggering voltage after actuation for a predetermined time, said power source, said two current conducting terminals and said time delay means connected in circuit, bistable switching means having an unlatched condition and a latched condition, commutating means and a line load impedance, said semiconductor connected to said time delay means, said time delay means connected to said bistable switching means, said bistable switching means connecting said telephone line with said line load impedance and connected to actuate said associated apparatus, said commutating means connected to said bistable switching means, a ringing voltage appearing in said telephone line, a fraction of said ringing voltage being applied to said control element and to said one of said current conducting terminals, causing current flow from said power source through said current conducting terminals to said time delay means, when said ringing voltage continues for said predetermined time, said time delay means producing said triggering voltage, said triggering voltage actuating said bistable switching means into said latched condition, said latched bistable switching means providing a dc path for said telephone line through said line load impedance, establishing line seizure and actuating said associated apparatus; a commutating impulse given to said commutating means causing said latched bistable switching means to return to said unlatched condition, opening said dc path, releasing line seizure and causing said associated apparatus to stop, said switch thereby being restored to standby condition.

Claim 3

In claim 1, a transforMer having a primary and a secondary, said primary connected in series with said capacitor across said telephone line, said secondary applying said fraction of said ringing voltage to said control element and to said one of said current conducting terminals.

Claim 4

In claim 2, a diode and a capacitor in circuit with said secondary, said diode and said capacitor together with said secondary comprising a time delay charging circuit, for input to said control element and said one of said current conducting terminals.

Claim 5

In claim 3, commutating means, said semiconductor comprising a pair of complementary NPN-PNP transistors in a regenerative feedback arrangement, each of said transistors having a base, a collector and an emitter, one of said bases corresponding to said control element, said emitters of said transistors corresponding to said current conducting terminals, said fraction of said ringing voltage applied to said diode and said capacitor, charging said capacitor in a time delay arrangement, said capacitor connected effectively to one of said bases and one of said emitters of said transistors causing said complementary pair to latch and current to flow through said complementary pair and said load impedance from said power source, said current flow being employed to establish line seizure and to actuate said associated apparatus, and at the end of an operating cycle, said commutating means causinG said complementary pair to unlatch, to release line seizure and to deactuate said associated apparatus.

Claim 6

In claim 3, commutating means, said semiconductor comprising a thyristor having a gate, an anode and a cathode, said gate corresponding to said control element, said anode and said cathode corresponding to said current conducting terminals, a second diode, said fraction of said ringing voltage applied to said diode and said capacitor, charging said capacitor, said second diode connected effectively between said capacitor and said gate, said ringing voltage traversing said second diode and going to said gate, said voltage rising after a predetermined period to cause said thyristor to latch and current to flow from said power source through said thyristor and said load impedance, said second diode preventing said capacitor from charging from said gate, said current being employed to establish line seizure and to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said thyristor to unlatch, releasing line seizure and deactuating said associated apparatus.

Claim 7

In claim 1, said semiconductor comprising a transistor having a base, a collector and an emitter, said base corresponding to said control element, said collector and said emitter corresponding to said current conducting terminals, said fraction of said ringing voltage applied to said base and said emitter, causing current flow from said power source through said transistor and said impedance.

Claim 8

In claim 6, an R-C time delay charging circuit, a bistable switch and commutating means, said collector, said emitter, said impedance and said R-C time delay charging circuit coupled across said power source, said current flow charging said R-C time delay charging circuit and after said ringing voltage continues for more than a predetermined time delay period, latching said bistable switch, said bistable switch in latched condition causing line seizure and actuation of said associated apparatus, and at the end of an operating cycle, said commutating means unlatching said bistable switch, releasing line seizure and deactuating said associated apparatus.

Claim 9

In claim 7, a second load impedance, said bistable switch comprising a thyristor having a gate, an anode and a cathode, a unijunction transistor having an emitter and two bases, said second load impedance in series with said thyristor and said power source, said emitter of said unijunction transistor being fed by said R-C charging circuit, said emitter firing after said predetermined time delay period, said unijuNction transistor sending a pulse to said gate of said thyristor, causing said thyristor to latch, said latched thyristor causing second current flow from said power source through said second load impedance, said second current flow being employed to establish line seizure and to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said thyristor to unlatch, to release line seizure and to deactuate said associated apparatus.

Claim 10

In claim 7, a second laod impedance, said bistable switch comprising a complementary pair of PNP-NPN transistors in regenerative feedback arrangement, each of said transistors having a base, a collector and an emitter, said emitters being in series with said second load impedance across said power source, one of said bases being effectively connected to said R-C time delay charging circuit, said charging circuit causing said complementary pair to latch after said predetermined time delay period, said complementary pair in latched condition causing second current flow from said power source through said complementary pair and said second load impedance, said second current flow causing line seizure and actuating said associated apparatus, and at the end of an operating cycle, said commutating means unlatching said complementary pair, releasing line seizure and deactuating said associated apparatus.

Claim 11

In claim 2, said load impedance comprising a thermal delay switch having output terminals, said fraction of said ringing voltage causing current flow from said power source through said current conducting terminals and said thermal delay switch, said output terminals closing after said ringing voltage is received for more than a predetermined period, causing line seizure and actuating associated apparatus.

Claim 12

In claim 2, said semiconductor comprising a transistor having a base, a collector and an emitter, said base corresponding to said control element, said collector and said emitter corresponding to said current conducting terminals, said load impedance comprising a relay, said relay in series with said transistor across said power source, said fraction of said ringing voltage applied to said base and said emitter causing current flow through said transistor, said current flow actuating said relay, said actuated relay causing line seizure and actuating said associated apparatus.

Claim 13

In claim 7, a second transistor having a base, a collector and an emitter, said bistable switch comprising a permanent magnet bistable relay having a first and second windings, said second transistor in series with said first winding and said power source, said R-C time delay charging circuit coupled to said base and emitter of said second transistor, said R-C time delay, after said ringing voltage continued for more than a predetermined period, causing second current flow through said second transistor and through said first winding, thereby causing said bistable relay to latch, said latched relay causing line seizure and actuation of said associated apparatus, at the end of an operating cycle, said commutating means applying an impulse to said second winding, unlatching said bistable relay, releasing line seizure and deactuating said associated apparatus.

Claim 14

In claim 3, a permanent magnet bistable relay having first and second windings, said semiconductor comprising a transistor having a base, a collector and an emitter, and commutating means, said base corresponding to said control element, said collector and said emitter corresponding to said current conducting terminals, said load impedance comprising said first winding of said relay, said first winding in series with said transistor and said power source, said capacitor coupled to said base and said emitter, said ringing voltage continuing for more than a predetermined time period, charging said capacitor, causing said transistor to conduct and current to flow through said first winding, causing said bistable relay to latch, said latched relay causing lIne seizure and actuation of said associated apparatus, at the end of an operating cycle, said commutating means applying an impulse to said second winding, unlatching said bistable relay, releasing line seizure and deactuating said associated apparatus.

Claim 15

In claim 7, said bistable switch comprising first and second transistors in a bistable multivibrator circuit, each of said transistors having a base, collector and emitter, said R-C time delay charging circuit coupled to said first transistor causing said first transistor to latch after said predetermined time delay period by effectively causing current flow to said base of said first transistor, causing said second transistor to turn off, said multivibrator, with said first transistor on, causing line seizure and actuation of said associated apparatus, at the end of an operating cycle, said commutating means applying an impulse to said multivibrator causing said first transistor to turn off and said second transistor to turn on, said multivibrator with said first transistor off, releasing line seizure and deactuating said associated apparatus.

Claim 16

In claim 7, a second load impedance, said bistable switch comprising a thyristor having a gate, an anode and a cathode, a second transistor having a base, a collector and an emitter, said second load impedance in series with said thyristor and said power source, said base of said second transistor being fed by said R-C time delay charging circuit, said second transistor being coupled to said gate of said thyristor, after said predetermined time delay period, said R-C circuit causing said second transistor to conduct sufficient current to said gate to cause said thyristor to latch, said latched thyristor causing second current flow from said power source through said second load impedance, said second current flow being employed to establish line seizure and to actuate said associated apparatus, at the end of an operating cycle, said commutating means unlatching said thyristor, releasing line seizure and deactuating said associated apparatus.

Claim 17

In claim 7, a second load impedance, said bistable switch comprising a thyristor having a gate, an anode and a cathode, a unijunction transistor having an emitter and two bases, said second load impedance in series with said anode and cathode of said thyristor across said telephone line, said emitter of said unijunction transistor being fed by said R-C charging circuit, said unijunction transistor being coupled to said gate of said thyristor, said emitter of said unijunction transistor firing after said predetermined time delay period, said unijunction transistor sending a pulse to said gate causing said thyristor to latch, said latched thyristor causing second current flow from said telephone line through said second load impedance providing a dc path for line seizure, said second current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means unlatching said thyristor, releasing line seizure and deactuating said associated apparatus.

Claim 18

In claim 7, a second load impedance, a unijunction transistor having an emitter and two bases, said bistable switch comprising a complementary pair of PNP-NPN transistors in regenerative feedback arrangemen each of said transistors having a base, a collector and an emitter, said second load impedance in series with said emitters of said complementary pair across said telephone line, said emitter of said unijunction transistor being fed by said R-C charging circuit, said unijunction transistor being coupled to one of said bases of said transistors in said complementary pair, said unijunction transistor emitter firing after said predetermined time delay period, said unijunction transistor sending a pulse to said one of said bases of said complementary pair, causing said complementary pair to latch, said latched complementary pair causing second current flow from said telephone line through said second load impedance, providing A dc path for line seizure, said second current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said complementary pair to unlatch, to release line seizure and to deactuate said associated apparatus.

Claim 19

In claim 3, commutating means, said semiconductor comprising a complementary pair of PNP-NPN transistors in regenerative feedback arrangement, each of said transistors having a base, a collector and an emitter, one of said bases corresponding to said control element, said emitters corresponding to said current conducting terminals, said emitters in series with said impedance across said telephone line, said fraction of said ringing voltage applied to said diode and said capacitor, charging said capacitor in a time delay arrangement, said capacitor connected effectively to one of said bases and one of said emiters, after a predetermined time delay period causing said complementary pair to latch and second current flow from said telephone line through said load impedance, providing a dc path for line seizure, said second current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said complementary pair to unlatch, to release line seizure and to deactuate said associated apparatus.

Claim 20

In claim 10, a thyristor having a gate, an anode and a cathode, commutating means, a second load impedance, said anode and cathode of said thyristor in series with said second load impedance across said telephone line, said output terminals effectively connected to said gate and said anode of said thyristor, after said ringing voltage is received for more than said predetermined period, said output terminals closing and causing said thyristor to latch, said latched thyristor causing second current flow from said telephone line through said second load impedance providing a dc path for line seizure, said second current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said thyristor to unlatch, releasing line seizure, and deactuating said associated apparatus.

Claim 21

In claim 3, commutating means, and a second diode, said semiconductor comprising a thyristor having a gate 3, an anode and a cathode, said gate corresponding to said control element, said anode and said cathode corresponding to said current conducting terminals, said anode and cathode in series with said load impedance across said telephone line, said second diode effectively between said capacitor and said gate, said fraction of said ringing voltage applied to said diode and said capacitor charging said capacitor, traversing said second diode and rising after a predetermined period to cause said thyristor to latch and current to flow from said telephone line through said load impedance providing a dc path for line seizure, said current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said thyristor to unlatch, releasing line seizure and deactuating said associated apparatus.

Claim 22

In claim 10, commutating means, a complementary pair of PNP-NPN transistors in regenerative feedback arrangement, each of said transistors having a base, a collector and an emitter, a second load impedance, said emitters of said complementary pair in series with said second load impedance across said telephone line, said output terminals effectively connected to one of said bases of said complementary pair and another available terminal of said complementary pair, after said ringing voltage is received for more than said predetermined period, said output terminals closing and causing said complementary pair to latch, said latched complementary pair causing second current flow from said telephone line through said second load impedance providing a dc path for line seizure, said second current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means causing said complementary pair to unlatch, to release line seizure and to deactuate said associated apparatus.

Claim 23

In claim 16, first and second capacitors, third and fourth load impedances, and second and third thyristors, said thyristor and said second and third thyristors in a tristable arrangement, each of said thyristors having a gate, an anode and a cathode, said second thyristor in series with said third load impedance across said power source, said third thyristor in series with said fourth load impedance across said power source, said first capacitor coupling said first and second thyristors at the juncture of said thyristors and said second and third load impedances, said second capacitor coupling said second and third thyristors at the juncture of said thyristors and said third and fourth load impedances, an impulse to said gate of said third thyristor causing said third thyristor to latch and third current to flow through said fourth load impedance, said third current flow being employed to actuate said associated apparatus for testing when said first thyristor is disconnected from circuit, an impulse to said gate of said second thyristor causing said second thyristor to conduct and to unlatch said first thyristor by discharging said first capacitor across said first thyristor and to unlatch said third thyristor by discharging said second capacitor across said third thyristor.

Claim 24

In claim 1, a transistor having a base, collector and an emitter, a diode having an anode and a cathode, said telephone line having a high resting voltage and a low talking voltage, said power source having a voltage intermediate between said resting voltage and said talking voltage, said associated apparatus in series with said collector and emitter across said power source, said anode and cathode of said diode oriented with respect to said telephone line and said base so that said diode is forward biased by said low talking voltage and reverse biased by said high resting voltage, said talking voltage forward biasing said diode and forward biasing said base, causing conduction of said transistor and actuation of said associated apparatus from said power source, said resting voltage reverse biasing said diode, removing current flow from said base, said transistor ceasing to conduct and deactuating said associated apparatus.

Claim 25

In claim 1, time delay means, commutating means, a latching semiconductor switch and a second load impedance, said time delay means fed by said semiconductor, said time delay means coupled to said latching semiconductor switch, said latching semiconductor switch in series with said second load impedance across said telephone line, after said ringing voltage continues for more than a predetermined period, said time delay means latching said latching semiconductor switch causing second current flow through said second load impedance from said telephone line providing a dc path for line seizure, said second current flow being employed to actuate said associated apparatus, at the end of an operating cycle, said commutating means unlatching said latching semiconductor switch, releasing line seizure and deactuating said associated apparatus.

Claim 26

In claim 5, a transistor having a base, an emitter and a collector, said associated apparatus in series with said emitter and collector across said power source, said base of said transistor being forward biased by said current flow through said load impedance, said transistor then conducting second current flow through, and operating said associated apparatus, when said thyristor is unlatched, said forward bias being removed, said transistor ceasing conduction and deactuating said associated apparatus.

Claim 27

In claim 24, a transistor having a base, an emitter and a collector, said associated apparatus in series with said emitter and said collector across said power source, said base of said transistor being forward biased by said current flow through said second load impedAnce, said transistor then conducting third current flow through, and operating said associated apparatus, when said latching semiconductor switch is unlatched, said forward bias being removed, said transistor ceasing conduction and said associated apparatus being deactuated.

Claim 28

In claim 1, said line load impedance comprising a resistor, said bistable switching means including second switching means, an amplifier having an audio output and a ground return, and a second capacitor, said second switching means and said resistor in series across said telephone line to establish and release line seizure, said output and said ground return of said amplifier coupled by said second capacitor to said resistor.

Claim 29

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears, comprising a ring detector, time delay means producing a triggering voltage after actuation for a predetermined time period, a latching semiconductor having a control element and two current conducting terminals, said latching semiconductor having a latched condition and an unlatched condition, a relay having a coil and contacts, a power source, a line load impedance and commutating means, said telephone line, said ring detector, said time delay means and said control element connected serially, said current conducting terminals and said coil connected in series across said power source, said commutating means connected to said latching semiconductor, said line load impedance and said contacts in series across said telephone line, a ringing voltage appearing in said telephone line being applied to said ring detector, said ring detector actuating said time delay means, when said ringing voltage continues for said predetermined time period, said time delay means producing said triggering voltage, said triggering voltage applied to said control element causing said latching semiconductor to latch and to cause a first current flow from said power source through said coil, said contacts closing causing a second current flow through said line load impedance, establishing line seizure, a commutating impulse given to said commutating means causing said latching semiconductor to unlatch into said unlatched condition, stopping said first current flow through said coil, said contacts opening, stopping said second current flow and releasing line seizure, said switch thereby being restored to standby.

Claim 30

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears, comprising a ring detector, time delay means producing a triggering voltage after actuation for a predetermined time period, a latching semiconductor having a control element and two current conducting terminals, said latching semiconductor having a latched condition and an unlatched condition, a relay having a coil and contacts, a power source, a line load impedance and commutating means, said telephone line, said ring detector, said time delay means and said control element connected serially, said current conducting terminals and said coil connected in series across said power source, said commutating means connected to said latching semiconductor, said line load impedance and said contacts in series across said telephone line, a ringing voltage appearing in said telephone line being applied to said ring detector, said ring detector actuating said time delay means, when said ringing voltage continues for said predetermined time period, said time delay means producing said triggering voltage, said triggering voltage applied to said control element causing said latching semiconductor to latch and to cause a first current flow from said power source through said coil, said contacts closing causing a second current flow through said line load impedance, establishing line seizure, a commutating impulse given to said commutating means causing said latching semiconductor to unlatch into said unlatched condition, stopping said first current flow through said coil, said contacts opening, stopping said second current flow and releasing line seizure, said switch thereby being restored to standby.

Claim 31

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears comprising a capacitor, a transformer having a primary and a secondary, a diode, a timing capacitor, a latching semiconductor having a control element and two current conducting terminals, said latching semiconductor having a latched condition and an unlatched condition, a relay having a coil and contacts, a power source, a line load impedance and commutating means, said capacitor and said primary connected reactively across said telephone line; said secondary, said diode and said timing capacitor in circuit with said control element with reference to one of said current conducting terminals, said current conducting terminals and said coil in series across said power source, said line load impedance in series with said contacts across said telephone line, said commutating means connected to said latching semiconductor, a ringing voltage appearing in said telephone line, a fraction of said ringing voltage appearing at said secondary and applied to said diode, said diode rectifying said fraction of said ringing voltage and charging said timing capacitor, when said ringing voltage continues for said predetermined time, said voltage across said timing capacitor reaching said triggering voltage and being applied to said control element, causing said latching semiconductor to latch and current to flow through said coil, said contacts closing and providing a dc path from said telephone line through said line load impedance, establishing line seizure, a commutating impulse given to said commutating means causing said latched semiconductor to unlatch into said unlatched condition, stopping current flow through said coil, said contacts opening said dc path and releasing line seizure, said switch thereby being restored to standby.

Claim 32

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears comprising a capacitor, a transformer having a primary and a secondary, a diode, a timing capacitor, a latching semiconductor having a control element and two current conducting terminals, said latching semiconductor having a latched condition and an unlatched condition, a relay having a coil and contacts, a power source, a line load impedance and commutating means, said capacitor and said primary connected reactively across said telephone line; said secondary, said diode and said timing capacitor in circuit with said control element with reference to one of said current conducting terminals, said current conducting terminals and said coil in series across said power source, said line load impedance in series with said contacts across said telephone line, said commutating means connected to said latching semiconductor, a ringing voltage appearing in said telephone line, a fraction of said ringing voltage appearing at said secondary and applied to said diode, said diode rectifying said fraction of said ringing voltage and charging said timing capacitor, when said ringing voltage continues for said predetermined time, said voltage across said timing capacitor reaching said triggering voltage and being applied to said control element, causing said latching semiconductor to latch and current to flow through said coil, said contacts closing and providing a dc path from said telephone line through said line load impedance, establishing line seizure, a commutating impulse given to said commutating means causing said latched semiconductor to unlatch into said unlatched condition, stopping current flow through said coil, said contacts opening said dc path and releasing line seizure, said switch thereby being restored to standby.

Claim 33

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears comprising a first and a second thyristor, each of said thyristors having a gate, an anode and a cathode, a line load impedance, a second load impedance, a capacitor, a power source, means to couple said telephone line to said gate of said first thyristor, said anode and said cathode of said first thyristor and said line load impedance in series across said telephone line, said anode and said cathode of said second thyristor in series with said second load impedance across said power source, said first and second thyristors coupled by said capacitor in a d.c. static switch arrangement, a ringing voltage appearing in said telephone line, a triggering voltage being applied by said means to couple said telephone line to said gate of said first thyristor, to said gate of said first thyristor, causing said first thyristor to latch and a first current to flow through said line load impedance and to establish line seizure, a commutating impulse given to said gate of said second thyristor causing said second thyristor to latch and to discharge said capacitor through said second thyristor across said first thyristor, causing said first thyristor to unlatch, releasing line seizure, said switch being restored to standby, said second thyristor then restoring to unlatched condition.

Claim 34

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears comprising a first and a second thyristor, each of said thyristors having a gate, an anode and a cathode, a line load impedance, a second load impedance, a capacitor, a power source, means to couple said telephone line to said gate of said first thyristor, said anode and said cathode of said first thyristor and said line load impedance in series across said telephone line, said anode and said cathode of said second thyristor in series with said second load impedance across said power source, said first and second thyristors coupled by said capacitor in a d.c. static switch arrangement, a ringing voltage appearing in said telephone line, a triggering voltage being applied by said means to couple said telephone line to said gate of said first thyristor, to said gate of said first thyristor, causing said first thyristor to latch and a first current to flow through said line load impedance and to establish line seizure, a commutating impulse given to said gate of said second thyristor causing said second thyristor to latch and to discharge said capacitor through said second thyristor across said first thyristor, causing said first thyristor to unlatch, releasing line seizure, said switch being restored to standby, said second thyristor then restoring to unlatched condition.

Claim 35

In claim 30, said first and second thyristors coupled by said capacitor in a flip flop arrangement.

Claim 36

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears and which may have an associated telephone set and for actuating associated apparatus comprising a ring detector, time delay means producing a triggering voltage after actuation for a predetermined time period, first, second and third thyristors, each of said thyristors having a gate, an anode and a cathode, a line load impedance, first and second capacitors, a second and a third load impedance, a power source, said telephone line, said ring detector, said time delay means and said gate of said first thyristor coupled serially, said anode and said cathode of said first thyristor and said line load impedance in series across said telephone line, said anode and said cathode of said seocnd thyristor in series with said second load impedance across said power source, said anode and said cathode of said third thyristor in series with said third load impedance across said power source, said first capacitor coupling said first thyristor to said second thyristor, said second capacitor coupling said second thyristor to said third thyristor, said three thyristors thereby coupled in a tristable arrangement, a ringing voltage appearing in said telephone line being applied to said ring detector, said ring detector actuating said time delay means, said ringing voltage continuing for said predetermined time, said time delay means producing said triggering voltage, said triggering voltage applied to said gate causing said first thyristor to latch and to cause a first current flow from said telephone line through said line load impedance, establishing line seizure, said first current flow which may be used for actuating said associated apparatus, a commutating impulse given to said gate of said second thyristor causing said second thyristor to latch and said first capacitor to be discharged across said first thyristor causing said first thyristor to unlatch; an actuating impulse given to said gate of said third thyristor causing said third thyristor to latch and a second current to flow from said power source through said third load impedance, said second current flow which may be employed to actuate said associated apparatus, a commutating impulse given to said gate of said second thyristor Causing said second thyristor to latch and said second capacitor to be discharged across said third thyristor, causing said third thyristor to unlatch, said second current flow to stop and said associated apparatus to be deactuated.

Claim 37

A ring responsive line seizure switch for a telephone line in which a ringing voltage appears and which may have an associated telephone set and for actuating associated apparatus comprising a ring detector, time delay means producing a triggering voltage after actuation for a predetermined time period, first, second and third thyristors, each of said thyristors having a gate, an anode and a cathode, a line load impedance, first and second capacitors, a second and a third load impedance, a power source, said telephone line, said ring detector, said time delay means and said gate of said first thyristor coupled serially, said anode and said cathode of said first thyristor and said line load impedance in series across said telephone line, said anode and said cathode of said seocnd thyristor in series with said second load impedance across said power source, said anode and said cathode of said third thyristor in series with said third load impedance across said power source, said first capacitor coupling said first thyristor to said second thyristor, said second capacitor coupling said second thyristor to said third thyristor, said three thyristors thereby coupled in a tristable arrangement, a ringing voltage appearing in said telephone line being applied to said ring detector, said ring detector actuating said time delay means, said ringing voltage continuing for said predetermined time, said time delay means producing said triggering voltage, said triggering voltage applied to said gate causing said first thyristor to latch and to cause a first current flow from said telephone line through said line load impedance, establishing line seizure, said first current flow which may be used for actuating said associated apparatus, a commutating impulse given to said gate of said second thyristor causing said second thyristor to latch and said first capacitor to be discharged across said first thyristor causing said first thyristor to unlatch; an actuating impulse given to said gate of said third thyristor causing said third thyristor to latch and a second current to flow from said power source through said third load impedance, said second current flow which may be employed to actuate said associated apparatus, a commutating impulse given to said gate of said second thyristor Causing said second thyristor to latch and said second capacitor to be discharged across said third thyristor, causing said third thyristor to unlatch, said second current flow to stop and said associated apparatus to be deactuated.