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US3791650A Expired / Lapsed US ⏱️ 0.0 years remaining

Simulated dice game and control circuit therefor

Assignee: Electronic Data Controls Corp
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Filing: 1972-05-15
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Granted: 1974-02-12
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Expires: 1992-05-15
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Abstract

Abstract A simulated dice game including a playing board on which is presented a display including lamps arranged in a pattern corresponding to the spot patterns on two dice. A manually operated switch button is provided to activate and deactivate pulse generating devices for each lamp arrangement, and the generated pulses are fed to counter circuits that are switched through a predetermined recurring sequence of operating states which selectively energize the lamps through output circuitry to show combinations of one to six lamps on each die. The pulse generating device produces triggering pulses at a relatively low frequency and at a constant repetition rate during activation thereof by the switch button and produces such pulses at a descending repetition rate upon deactivation thereof by the switch button whereby the lamps flash visibly during activation and continue to flash at a descending repetition rate upon deactivation until a final operating state is displayed upon cessation of pulse generation.

Inventors

  • 👤 D Dice

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 02:49
CPC Classifications
G; G07; G07C; G07C15/00; G07C15/006; A; A63; A63F; A63F9/00; A63F9/04; A63F9/0468

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 299 words
An amusement device for producing one of a plurality of possible output indications selected by chance, including, in combination, manual switch means operable between activating and deactivating positions; pulse generating means connected to said switch means for activation and deactivation thereby, said pulse generating means producing triggering pulses at a constant repetition rate during activation thereof by said switch means and for producing triggering pulses at a descending repetition rate following deactivation thereof by said switch means and said pulse generating means including a programmable unijunction transistor having a ground connection to the cathode thereof, means for supplying the anode of said transistor with a supply voltage, means for imposing a bias voltage in the gate of said transistor, and selectively operable means including said switch means for imposing bias voltage on the gate of said transistor for establishing a voltage differential at which the anode voltage exceeds the gate voltage sufficiently to cause the transistor to commence generating pulses at a constant rate, and for decreasing said voltage differential at a predetermined rate until said voltage differential is substantially zero whereupon said transistor will cease generating pulses, said predetermined rate of decreasing said voltage differential being sufficiently slow to result in said transistor generating pulses at a descending repetition rate beginning at said constant repetition rate and progressing through a plurality of different repetition rates until no pulses are generated; counter circuit means connected to said pulse generating means and operable to be switched through a predetermined recurring sequence of operating states by pulses received from said pulse generating means and operable to remain in an operating state in the absence of said pulses; and output means connected to said counter circuit means and operable to provide an indication of the operating state of said counter circuit means.
Claim 2
Dependent Claim 299 words
An amusement device for producing one of a plurality of possible output indications selected by chance, including, in combination, manual switch means operable between activating and deactivating positions; pulse generating means connected to said switch means for activation and deactivation thereby, said pulse generating means producing triggering pulses at a constant repetition rate during activation thereof by said switch means and for producing triggering pulses at a descending repetition rate following deactivation thereof by said switch means and said pulse generating means including a programmable unijunction transistor having a ground connection to the cathode thereof, means for supplying the anode of said transistor with a supply voltage, means for imposing a bias voltage in the gate of said transistor, and selectively operable means including said switch means for imposing bias voltage on the gate of said transistor for establishing a voltage differential at which the anode voltage exceeds the gate voltage sufficiently to cause the transistor to commence generating pulses at a constant rate, and for decreasing said voltage differential at a predetermined rate until said voltage differential is substantially zero whereupon said transistor will cease generating pulses, said predetermined rate of decreasing said voltage differential being sufficiently slow to result in said transistor generating pulses at a descending repetition rate beginning at said constant repetition rate and progressing through a plurality of different repetition rates until no pulses are generated; counter circuit means connected to said pulse generating means and operable to be switched through a predetermined recurring sequence of operating states by pulses received from said pulse generating means and operable to remain in an operating state in the absence of said pulses; and output means connected to said counter circuit means and operable to provide an indication of the operating state of said counter circuit means.
Claim 3
Dependent Claim 103 words
An amusement device as defined in claim 1 and further characterized in that said selectively operable means includes said switch means and a gate biasing circuit which includes a voltage source and a resistor-capacitor timing circuit, said switch means being selectively operable between a first position at which said transistor gate is effectively grounded whereby the voltage at said gate is reduced and a second position at which said resistor-capacitor timing circuit is in circuit with said gate whereby said voltage at said gate is progressively increased as said capacitor charges until the voltage at said gate is sufficient to disable said transistor.

References Cited (Backward Citations)

GB1107552A Cited
US3357703A Cited
US3439281A Cited
US3580581A Cited
US3592473A Cited
US3659853A Cited
US3633128A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-02-11 1977-08-13 1978-02-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-02-11 1981-08-13 1982-02-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-02-11 1985-08-13 1986-02-12 $7700.00 Window Closed / Lapsed

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