US3790897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential amplifier and bias circuit
Assignee: RCA Licensing Corp
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Filing: 1971-04-05
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Granted: 1974-02-05
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Expires: 1991-04-05
Abstract
Abstract Differential amplifier having reduced static and cross modulation errors. The amplifier includes first and second pairs of transistors, the emitters of each pair being connected to first and second current sources, respectively. A first additional transistor is connected at its emitter to the base of one transistor from each pair and at its base to the collector of one transistor from the first pair for forming a first input terminal. A second additional transistor is connected at its emitter to the base of the remaining transistors from each pair and at its base to the collector of the other transistor from the first pair for forming a second input terminal. A current signal is applied across the input terminals for controlling the subdivision of the current from the first current source between the two transistors of the first pair thereby controlling the subdivision of the current from the second current source between the two transistors of the second pair.
Inventors
- 👤 C Wheatley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:39
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; H03F3/34; H03F3/343; H03G; H03G1/00; H03G1/0005; H03G1/0017; H03G1/0023; H03F2203/00; H03F2203/45; H03F2203/45024; H03F2203/45031; H03F2203/45178; H03F2203/45188
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
269 words
In combination: first and second substantially constant current sources, each having two terminals; first and second semiconductor devices, each device having a conduction path and a control electrode for controlling the conductivity of said conduction path; means connecting one end of each conduction path to one of the two terminals of said first current source for carrying its source current and means for coupling the other end of each conduction path to a first voltage terminal for receiving a potential, the other one of the two terminals of said first current source being connected to a second voltage terminal for receiving a potential; first and second means, each means comprising first and second transistors, the base of the first transistor being connected to the emitter Of the second transistor, the emitter of the first transistor being connected to one of said two terminals of said second current source, and the collector of the first transistor being connected to the base of the second transistor; the base of the first transistor of the first means being connected to the control electrode of said first semiconductor device and the base of the first transistor of the second means being connected to the control electrode of said second semiconductor device; two input terminals adapted to receive input signals, one input terminal connected to the base of the second transistor of said first means and the other input terminal connected to the base of the second transistor of said second means; and means for coupling the collector electrodes of the second transistors of said first and second means to said first voltage terminal.
Claim 2
Dependent Claim
269 words
In combination: first and second substantially constant current sources, each having two terminals; first and second semiconductor devices, each device having a conduction path and a control electrode for controlling the conductivity of said conduction path; means connecting one end of each conduction path to one of the two terminals of said first current source for carrying its source current and means for coupling the other end of each conduction path to a first voltage terminal for receiving a potential, the other one of the two terminals of said first current source being connected to a second voltage terminal for receiving a potential; first and second means, each means comprising first and second transistors, the base of the first transistor being connected to the emitter Of the second transistor, the emitter of the first transistor being connected to one of said two terminals of said second current source, and the collector of the first transistor being connected to the base of the second transistor; the base of the first transistor of the first means being connected to the control electrode of said first semiconductor device and the base of the first transistor of the second means being connected to the control electrode of said second semiconductor device; two input terminals adapted to receive input signals, one input terminal connected to the base of the second transistor of said first means and the other input terminal connected to the base of the second transistor of said second means; and means for coupling the collector electrodes of the second transistors of said first and second means to said first voltage terminal.
Claim 3
Dependent Claim
69 words
The combination as claimed in claim 1 wherein each one of said semiconductor device is a transistor having a collector, an emitter, and a base, and wherein the collector-to-emitter path of a transistor is said conduction path of said device and wherein saidbase is said control electrode and wherein the emitters of said semiconductor devices are connected to said one of the two terminals of said first current source.
Claim 4
Dependent Claim
30 words
The combination as claimed in claim 1 including means for supplying an input signal current to one of the input terminals and a reference potential to the other input terminal.
Claim 5
Dependent Claim
208 words
The combination comprising: first and second current sources, each source having two terminals; first, second, third, fourth, fifth, and sixth transistors, each having a base, an emitter, and a collector; means connecting the emitters of said first and second transistors to one terminal of said first current source; means connecting the emitters of said third and fourth transistors in common to one terminal of said second current source; means direct current connecting the emitter of said fifth transistor to the bases of said first and third transistors, and means direct current connecting the emitter of said sixth transistor to the bases of said second and fourth transistors; first and second terminals for the application of signals; means direct current connecting the base of said fifth transistor and the collector of said third transistor to said first terminal, and means direct current connecting the collector of said fourth transistor and the base of said sixth transistor to said second terminal; first and second output load means connected between the collectors of said first and second transistors, respectively, and a point of potential; and means for coupling the collectors of the fifth and sixth transistors to the other ones of said two terminals of said first and second current sources.
Claim 6
Dependent Claim
208 words
The combination comprising: first and second current sources, each source having two terminals; first, second, third, fourth, fifth, and sixth transistors, each having a base, an emitter, and a collector; means connecting the emitters of said first and second transistors to one terminal of said first current source; means connecting the emitters of said third and fourth transistors in common to one terminal of said second current source; means direct current connecting the emitter of said fifth transistor to the bases of said first and third transistors, and means direct current connecting the emitter of said sixth transistor to the bases of said second and fourth transistors; first and second terminals for the application of signals; means direct current connecting the base of said fifth transistor and the collector of said third transistor to said first terminal, and means direct current connecting the collector of said fourth transistor and the base of said sixth transistor to said second terminal; first and second output load means connected between the collectors of said first and second transistors, respectively, and a point of potential; and means for coupling the collectors of the fifth and sixth transistors to the other ones of said two terminals of said first and second current sources.
Claim 7
Dependent Claim
28 words
The combination as claimed in claim 4 wherein said first current source is a variable current source and wherein said second current source is a constant current source.
Claim 8
Dependent Claim
15 words
The combination as claimed in claim 4 wherein said current sources are variable current sources.
Claim 9
Dependent Claim
18 words
The combination as claimed in claim 4 wherein said transistors are bipolar transistors of the same conductivity type.
Claim 10
Dependent Claim
47 words
The combination as claimed in claim 5 wherein the signal applied to said first terminal is a current, wherein a reference potential is applied to the second input terminal and wherein the potential applied to the collectors of said fifth and sixth transistors is a fixed potential.
Claim 11
Dependent Claim
60 words
The combination as claimed in claim 5 wherein the means coupling the emitter of said fifth transistor to the bases of said first and third transistors includes at least one forward biased diode and wherein the means coupling the emitter of said sixth transistor to the bases of said second and fourth transistors include at least one forward biased diode.
Claim 12
Dependent Claim
209 words
The combination comprising: first and second substantially constant current sources, each source having two terminals; A first difference amplifier stage comprising first and second transistors having their emitters connected in common to one terminal of said first current source; first and second input terminals for the application of signals thereto to be amplified by said difference amplifier stage; a third transistor having its base connected to said first input terminal and its emitter to the base of said first transistor and a fourth transistor having its base connected to said second input terminal and its emitter to the base of said second transistor; means for controlling the amplification of said difference amplifier stage comprising fifth and sixth transistors having their emitters connected in common to one terminal of said second constant current source with the base of said fifth transistor connected to the base of said first transistor and its collector to said first input terminal and with the base of said sixth transistor connected to the base of said second transistor and its collector to the second input terminal; and means for coupling the collectors of said first, second, third and fourth transistors to the other ones of said two terminals of said first and second current sources.
Claim 13
Dependent Claim
209 words
The combination comprising: first and second substantially constant current sources, each source having two terminals; A first difference amplifier stage comprising first and second transistors having their emitters connected in common to one terminal of said first current source; first and second input terminals for the application of signals thereto to be amplified by said difference amplifier stage; a third transistor having its base connected to said first input terminal and its emitter to the base of said first transistor and a fourth transistor having its base connected to said second input terminal and its emitter to the base of said second transistor; means for controlling the amplification of said difference amplifier stage comprising fifth and sixth transistors having their emitters connected in common to one terminal of said second constant current source with the base of said fifth transistor connected to the base of said first transistor and its collector to said first input terminal and with the base of said sixth transistor connected to the base of said second transistor and its collector to the second input terminal; and means for coupling the collectors of said first, second, third and fourth transistors to the other ones of said two terminals of said first and second current sources.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-04 | 1977-08-06 | 1978-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-04 | 1981-08-06 | 1982-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-04 | 1985-08-06 | 1986-02-05 | $7700.00 | Window Closed / Lapsed |