US3790893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample and hold circuit for digital signals
Assignee: AT&T Inc
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Filing: 1972-11-16
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Granted: 1974-02-05
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Expires: 1992-11-16
Abstract
Abstract A sample and hold circuit wherein the digital signal to be sampled is differentially applied to a pair of gated transistors. Once during each time slot, the transistor pair is gated to provide a sampling aperture during which an integration of the digital signal is performed. The results of each integration are evaluated to determine whether a pulse (or a space) occurred in the digital signal during the time slot.
Inventors
- 👤 W Corwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:43
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
153 words
In a digital transmission system operating on digital signals occupying predetermined time slots, a digital signal regenerator comprising sampling means having a sampling interval with a duration equal to a substantial portion of the duration of a time slot, said digital signals being coupled to said sampling means; linear means for linearly integrating the output of said sampling means to obtain an integral indicative of the digital signal within the duration of the sampling interval; bistable means for rapidly assuming a state in response to the integral and maintaining the assumed state for a duration of a time slot to produce an output signal indicative of the presence of a pulse during the sampling interval; and pulsing means for resetting said linear means by supplying a current pulse thereto after said bistable means assumes a state in response to the integral so that said integral is eliminated before the next successive sampling interval.
Claim 2
Dependent Claim
153 words
In a digital transmission system operating on digital signals occupying predetermined time slots, a digital signal regenerator comprising sampling means having a sampling interval with a duration equal to a substantial portion of the duration of a time slot, said digital signals being coupled to said sampling means; linear means for linearly integrating the output of said sampling means to obtain an integral indicative of the digital signal within the duration of the sampling interval; bistable means for rapidly assuming a state in response to the integral and maintaining the assumed state for a duration of a time slot to produce an output signal indicative of the presence of a pulse during the sampling interval; and pulsing means for resetting said linear means by supplying a current pulse thereto after said bistable means assumes a state in response to the integral so that said integral is eliminated before the next successive sampling interval.
Claim 3
Dependent Claim
39 words
The regenerator as claimed in claim 1, wherein said sampling means further comprises second pulsing means for producing a pulse to define a sampling interval of a duration that is at least one-half the duration of said time slot.
Claim 4
Dependent Claim
76 words
The regenerator as claimed in claim 1, wherein said sampling means comprises first and second transistors having complementary digital signals respectively applied to their bases such that said first and second transistors are differentially controlled by said complementary digital signaLs, and said second pulsing means coupled to the emitters of said first and second transistors, said second pulsing means producing a pulse of operating current for said first and second transistors to control the sampling interval.
Claim 5
Dependent Claim
65 words
The regenerator as claimed in claim 3, wherein said linear means comprises first capacitive means connected to the collector of said first transistor and second capacitive means connected to the collector of said second transistor, the differential charge stored by said first and second capacitive means forming an integral indicative of the digital signal applied to said regenerator during the occurrence of the sampling interval.
Claim 6
Dependent Claim
42 words
The regenerator as claimed in claim 4 including diode means connected from said first and second capacitive means to said pulsing means and being operative in response to a pulse from the pulsing means to reset said first and second capacitive means.
Claim 7
Dependent Claim
35 words
The regenerator as claimed in claim 3 wherein said first and second transistors have first any second resistive elements in series with their emitters to insure linear operation of said transistors during the sampling interval.
Claim 8
Dependent Claim
136 words
In a digital transmission system operating on digital signals occupying predetermined time slots, a digital signal regenerator comprising: generator means for producing a current pulse having a duration equal to a substantial portion of a time slot; linear means for integrating the digital signal during the interval determined by the duration of said current pulse, said linear means storing an integral which is a portion of said current pulse, the magnitude of said integral being controlled by the digital signal present during said interval; nonlinear means comprising a bistable circuit for evaluating said integral to produce an output signal indicative of the presence of a pulse during said interval; and pulsing means for resetting said linear means after said nonlinear means evaluates said integral so that said integral is eliminated before the next successive integrating interval.
Claim 9
Dependent Claim
136 words
In a digital transmission system operating on digital signals occupying predetermined time slots, a digital signal regenerator comprising: generator means for producing a current pulse having a duration equal to a substantial portion of a time slot; linear means for integrating the digital signal during the interval determined by the duration of said current pulse, said linear means storing an integral which is a portion of said current pulse, the magnitude of said integral being controlled by the digital signal present during said interval; nonlinear means comprising a bistable circuit for evaluating said integral to produce an output signal indicative of the presence of a pulse during said interval; and pulsing means for resetting said linear means after said nonlinear means evaluates said integral so that said integral is eliminated before the next successive integrating interval.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-04 | 1977-08-06 | 1978-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-04 | 1981-08-06 | 1982-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-04 | 1985-08-06 | 1986-02-05 | $7700.00 | Window Closed / Lapsed |