Clock pulse regenerating circuit for demodulating input pulse signal having uneven time pulse distribution

Claim 2

A clock pulse regenerating circuit for demodulating an input pulse signal having an uneven pulse distribution in the time domain comprising; means for deriving clock pulses from said input pulse signal, means coupled to said clock pulse derivation means for delaying said clock pulses a predetermined period of time, and means for detecting the absence of pulses in said input pulse signal for at least a predetermined time interval, said clock pulse derivation means being responsive to said detecting means for reproducing the last delayed clock pulse when said input pulse signal is absent pulses for at least said predetermined time interval at a repetition rate determined by said delay means, wherein said detecting means comprises first logic means responsive to said delayed clock pulses for producing an enable signal in response to the receipt of a delayed clock pulse after said predetermined time interval, said means for deriving clock pulses comprising second logic means, for reporducing the last delayed clock pulse in response to said enable signal, and counter means for counting the number of derived clock pulses and an inhibit signal generation means, responsive to a predetermined count in said counter means, for producing an inhibit signal, said first logic means being responsive to said inhibit signal whereby the generation of an enable signal is prevented during the existence of said inhibit signal.

Claim 3

The clock pulse regenerating circuit of claim 1 further including means for resetting said counter means in response to the receipt of a pulse in said input pulse signal.

Claim 4

The clock pulse regenerating circuit of claim 1 further comprising an oscillator circuit including a phase detector and voltage controlled oscillator coupled to said clock pulse deriving means.

Claim 5

A clock pulse regenerating circuit for demodulating an input pulse signal having an uneven pulse distribution in the time domain comprising; means for deriving clock pulses from said input pulse signal, means coupled to said clock pulse derivation means for delaying said clock pulses a predetermined period of time, and means for detecting the absence of pulses in said input pulse signal for at least a predetermined time interval, said clock pulse derivation means being responsive to said detecting means for reproducing the last delayed clock pulse when said input pulse signal is absent pulses for at least said predetermined time interval at a repetition rate determined by said delay means, wherein said detecting means comprises first logic means responsive to said delayed clock pulses for producing an enable signal in response to the receipt of a delayed clock pulse after said predetermined time interval and an inhibit-reset circuit coupled to said first logic means for controlling the duration of said predetermined time interval, said means for deriving clock pulses comprising second logic means, for reproducing the last delayed clock pulse in response to said enable signal, and wherein said first and second logic means comprise NAND gates and said inhibit-reset circuit comprises a monostable multivibrator producing an inhibit signal lasting said predetermined time interval to disable the NAND gate comprising said first logic means whereby the generation of said enable signal is prevented during the existence of said inhibit signal.

Claim 6

A clock pulse regenerating circuit for demodulating an input pulse signal having an uneven pulse distribution in the time domain comprising; means for deriving clock pulses from said input pulse signal, means coupled to said clock pulse derivation means for delaying said clock pulses a predetermined period of time, and means for detecting the absence of pulses in said input pulse signal for at least a predetermined time interval, said clock pulse derivation means being responsive to said detecting means for reproducing the last delayed clock pulse when said input pulse signal is absent pulses for at least said predetermined time interval at a repetition rate determined by said delay means, wherein said detecting means comprises first logic means responsive to said delayed clock pulses for producing an enable signal in response to the receipt of a delayed clock pulse after said predetermined time interval and an inhibit-reset circuit coupled to said first logic means for controlling the duration of said predetermined time interval, said means for deriving clock pulses comprising second logic means, for reproducing the last delayed clock pulse in response to said enable signal, and wherein said first and second logic means comprise NAND gates and said inhibit-reset circuit comprises a monostable multivibrator producing an inhibit signal lasting said predetermined time interval to disable the NAND gate comprising said first logic means whereby the generation of said enable signal is prevented during the existence of said inhibit signal.