Frame synchronization system

Claim 2

A dual decision circuit to provide a pair of control signals each having a first condition when an input signal is in a first condition for a first predetermined length of time and a second condition when said input signals is in a second condition for a second predetermined length of time different than said first predetermined length of time comprising: a first source of said input signal; first means coupled to said first source having a first, relatively long time constant equal to said first predetermined length of time and a reference operating level; second means coupled to said first source having a second, relatively short time constant producing one of said pair of control signals; third means coupled to said first and second means to produce the other of said pair of control signals; and a unidirectional device coupled between said third means and said first means, said unidirectional device being responsive to said other of said pair of control signals when it is in said first condition to reset said first means to said reference operating level.

Claim 3

A dual decision circuit to provide a pair of control signals each having a first condition when an input signal is in a first condition for a first predetermined length of time and a second condition when said input signal Is in a second condition for a second predetermined length of time different than said first predetermined length of time comprising: a first source of said input signal; first means coupled to said first source having a first, relatively long time constant equal to said first predetermined length of time and a reference operating level; second means coupled to said first source having a second, relatively short time constant producing one of said pair of control signals; and third means coupled to said first and second means to produce the other of said pair of control signals and to reset said first means to said reference operating level when said other of said pair of control signals is in said first condition; said first means including a first integrator coupled to said first source having said first time constant and said reference operating level, and a first amplitude comparator coupled to the output of said first integrator; said second means including a second integrator coupled to said first source having said second time constant, a second amplifier comparator coupled to the output of said second integrator to produce said one of said pair of control signals, and a third amplitude comparator coupled to the output of said second integrator; and said third means including a bistable means coupled to the output of said first and third comparators to produce said other of said pair of control signals, and a unidirectional device coupled between the output of said bistable means and the input of said first integrator to reset said first integrator to said reference operating level when said other of said pair of control signals is in said first condition.

Claim 4

A dual decision circuit to provide a pair of control signals each having a first condition when an input signal is in a first condition for a first predetermined length of time and a second condition when said input signal Is in a second condition for a second predetermined length of time different than said first predetermined length of time comprising: a first source of said input signal; first means coupled to said first source having a first, relatively long time constant equal to said first predetermined length of time and a reference operating level; second means coupled to said first source having a second, relatively short time constant producing one of said pair of control signals; and third means coupled to said first and second means to produce the other of said pair of control signals and to reset said first means to said reference operating level when said other of said pair of control signals is in said first condition; said first means including a first integrator coupled to said first source having said first time constant and said reference operating level, and a first amplitude comparator coupled to the output of said first integrator; said second means including a second integrator coupled to said first source having said second time constant, a second amplifier comparator coupled to the output of said second integrator to produce said one of said pair of control signals, and a third amplitude comparator coupled to the output of said second integrator; and said third means including a bistable means coupled to the output of said first and third comparators to produce said other of said pair of control signals, and a unidirectional device coupled between the output of said bistable means and the input of said first integrator to reset said first integrator to said reference operating level when said other of said pair of control signals is in said first condition.

Claim 5

A circuit according to claim 2, wherein each of said integrators and each of said comparators include an operational amplifier.

Claim 6

A circuit according to claim 2, wherein said bistable means includes a flip flop having its ''''1'''' input coupled to the output of said first comparator, its ''''0'''' input coupled to the output of said third comparator and its ''''1'''' output producing said other of said pair of control signals; and said unidirectional device including a diode coupled between the ''''0'''' output of said flip flop and the input of said first integrator, said diode being poled to be reverse biased when said other of said pair of control signals is in said second condition and forward biased when said other of said pair of control signals is in said first condition to reset said first integrator to said reference operating level.

Claim 7

A dual decision circuit to provide a pair of control signals each having a first condition when an input signal is in a first condition for a first predetermined length of time and a second condition when said input signal is in a second condition for a second predetermined length of time different than said first predetermined length of time comprising: a first source of said input signal; first means coupled to said first source having a first, relatively long time constant equal to said first predetermined length of time and a reference operating level; second means coupled to said first source having a second, relatively short time constant producing one of said pair of control signals; and third means coupled to said first and second means to produce the other of said pair of control signals and to reset said first means to said reference operating level when said other of said pair of control signals is in said first condition; said first means including a second source of bias voltage, a first resistor coupled to said first source, a first operating amplifier having an inverting input coupled to said first resistor, a non-inverting input coupled to said second source, and an output, a first capacitor coupled between said output and said inverting input of said first amplifier, said first amplifier having said reference operatinG level, said first resistor and said first capacitor providing said first time constant, a third source of bias voltage, and a second operational amplifier having an inverting input coupled to said output of said first amplifier, a non-inverting input coupled to said third source, and an output; said second means including a fourth source of bias voltage, a second resistor coupled to said first source, a third operational amplifier having an inverting input coupled to said second resistor, a non-inverting input coupled to said fourth source, and an output, a second capacitor coupled between said output and said inverting input of said third amplifier, said second resistor and said second capacitor providing said second time constant, a clamp circuit coupled in parallel with said second capacitor, a fifth source of bias voltage, a fourth operational amplifier having an inverting input coupled to said fifth source, a non-inverting input coupled to said output of said third amplifier, and an output, a sixth source of bias voltage, and a fifth operational amplifier having an inverting input coupled to said output of said third amplifier, a non-inverting input coupled to said sixth source, and an output providing said one of said pair of control signals; and said third means including a flip flop having a ''''1'''' input coupled to said output of said second amplifier, a ''''0'''' input coupled to said output of said fourth amplifier, a ''''1'''' output to produce said other of said pair of control signals, and a ''''0'''' output, and a diode coupled between said ''''0'''' output and said inverting input of said first amplifier, said diode being poled to be reverse biased when said other of said pair of control signals is in said second condition and forward biased when said other of said pair of control signals is in said first condition to reset said first amplifier to said reference operating level.

Claim 8

A dual decision circuit to provide a pair of control signals each having a first condition when an input signal is in a first condition for a first predetermined length of time and a second condition when said input signal is in a second condition for a second predetermined length of time different than said first predetermined length of time comprising: a first source of said input signal; first means coupled to said first source having a first, relatively long time constant equal to said first predetermined length of time and a reference operating level; second means coupled to said first source having a second, relatively short time constant producing one of said pair of control signals; and third means coupled to said first and second means to produce the other of said pair of control signals and to reset said first means to said reference operating level when said other of said pair of control signals is in said first condition; said first means including a second source of bias voltage, a first resistor coupled to said first source, a first operating amplifier having an inverting input coupled to said first resistor, a non-inverting input coupled to said second source, and an output, a first capacitor coupled between said output and said inverting input of said first amplifier, said first amplifier having said reference operatinG level, said first resistor and said first capacitor providing said first time constant, a third source of bias voltage, and a second operational amplifier having an inverting input coupled to said output of said first amplifier, a non-inverting input coupled to said third source, and an output; said second means including a fourth source of bias voltage, a second resistor coupled to said first source, a third operational amplifier having an inverting input coupled to said second resistor, a non-inverting input coupled to said fourth source, and an output, a second capacitor coupled between said output and said inverting input of said third amplifier, said second resistor and said second capacitor providing said second time constant, a clamp circuit coupled in parallel with said second capacitor, a fifth source of bias voltage, a fourth operational amplifier having an inverting input coupled to said fifth source, a non-inverting input coupled to said output of said third amplifier, and an output, a sixth source of bias voltage, and a fifth operational amplifier having an inverting input coupled to said output of said third amplifier, a non-inverting input coupled to said sixth source, and an output providing said one of said pair of control signals; and said third means including a flip flop having a ''''1'''' input coupled to said output of said second amplifier, a ''''0'''' input coupled to said output of said fourth amplifier, a ''''1'''' output to produce said other of said pair of control signals, and a ''''0'''' output, and a diode coupled between said ''''0'''' output and said inverting input of said first amplifier, said diode being poled to be reverse biased when said other of said pair of control signals is in said second condition and forward biased when said other of said pair of control signals is in said first condition to reset said first amplifier to said reference operating level.