US3789247A
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US
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Dynamically ordered bidirectional shift register having charge coupled devices
Assignee: International Business Machines Corp
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Filing: 1972-07-03
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Granted: 1974-01-29
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Expires: 1992-07-03
Abstract
Abstract The specification describes charge coupled devices in a bidirectional shift register and having a dynamic ordering capability. Charge coupled devices are shown in a semiconductor structure with FET amplifying circuits, uniquely adapted for bidirectional operation by means of a circuit which changes the order of occurrence of the clocking pulses. The density of charge coupled devices is preserved together with improved access time resulting from bidirectional operation and dynamic ordering.
Inventors
- 👤 W Beausoleil
- 👤 I Ho
- 👤 H Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:28
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/007; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C19/287; H; H10; H10D; H10D84/00; H10D84/891
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
214 words
A charge coupled device shift register formed in a semiconductor substrate comprising: a plurality of charge coupled shift register bit positions arranged in a series bit stream formed in the semiconductor substrate, and responsive to a source of clock pulses for shifting data bits in a first of two possible directions; first means connected between said source of clock pulses and said plurality of charge coupled shift register bit positions, responsive to said source of clock pulses and also responsive to one of two mutually exclusive shift direction pulses for selectively altering the order of occurrence of said clock pulses, thereby changing the direction of shifting said series bit stream; bidirectional amplifying means integral with said same semiconductor substrate electrically connected in the series bit stream, for amplifying the data bits, and responsive to a source of gating pulses for amplifying data bits being shifted in a first of two possible directions; second means connected between said source of gating pulses and said bidirectional amplifying means, responsive to said source of gating pulses and also responsive to the same one of said two mutally exclusive shift direction pulses for selectively altering the order of occurrence of said gating pulses, thereby amplifying data bits in the same direction as shifted in the series bit stream.
Claim 2
Dependent Claim
214 words
A charge coupled device shift register formed in a semiconductor substrate comprising: a plurality of charge coupled shift register bit positions arranged in a series bit stream formed in the semiconductor substrate, and responsive to a source of clock pulses for shifting data bits in a first of two possible directions; first means connected between said source of clock pulses and said plurality of charge coupled shift register bit positions, responsive to said source of clock pulses and also responsive to one of two mutually exclusive shift direction pulses for selectively altering the order of occurrence of said clock pulses, thereby changing the direction of shifting said series bit stream; bidirectional amplifying means integral with said same semiconductor substrate electrically connected in the series bit stream, for amplifying the data bits, and responsive to a source of gating pulses for amplifying data bits being shifted in a first of two possible directions; second means connected between said source of gating pulses and said bidirectional amplifying means, responsive to said source of gating pulses and also responsive to the same one of said two mutally exclusive shift direction pulses for selectively altering the order of occurrence of said gating pulses, thereby amplifying data bits in the same direction as shifted in the series bit stream.
Claim 3
Dependent Claim
61 words
A charge coupled device shift register as in claim 1 wherein said first means comprises: a plurality of gating circuits responsive to at least two of said plurality of clock pulses and also reponsive to the one of two mutally exclusive shift direction pulses for interchaning the time of occurrence of said at least two of said plurality of clock pulses.
Claim 4
Dependent Claim
61 words
A charge coupled device shift register as in claim 1 wherein said second means comprises: a plurality of gating circuits responsive to at least two of said plurality of gating pulses and also responsive to the one of two mutually exclusive shift direction pulses for interchanging the time of occurrence of said at least two of said plurality of gating pulses.
Claim 5
Dependent Claim
289 words
A bidirectional CCD shift register system having a dynamic ordering capability for storing electronic data and for rapid accessing of sad data, including at least two sections of operatively interconnected shft register blocks, the first one of said sections having a large number of shift register blocks for storing the bulk of said data, the second one of said at least two sections having a disparately small number of shift register blocks for storing high priority data, each of said shift register blocks comprising; a plurality of charge coupled shift register bit positions arranged in a series bit stream formed in a semiconductor substrate, and responsive to a source of clock pulses providing a plurality of clock pulses for shifting data bits in a first of two possible directions; first means connected between said source of clock pulses and said plurality of charge coupled shift register bit positions, responsive to said source of clock pulses and also responsive to one of two mutually exclusive shift direction pulses for selectively altering the time of occurrence of said clock pulses, thereby changing the direction of shifting said data bits; bidirectional amplifying means integral with said same semiconductor substrate electrically connected in the series bit stream, for amplifying the data bits; a source of gating pulses; second means connected between said source of gating pulses and said bidirectional amplifying means, responsive to said source of gating pulses and also responsive to the same one of said two mutually exclusive shift direction pulses for selectively altering the time occurrence of said gating pulses, thereby amplifying data bits in the same direction as shifted in the series bit stream, independently in each of said at least two sections of operatively interconnected shift reGister blocks.
Claim 6
Dependent Claim
289 words
A bidirectional CCD shift register system having a dynamic ordering capability for storing electronic data and for rapid accessing of sad data, including at least two sections of operatively interconnected shft register blocks, the first one of said sections having a large number of shift register blocks for storing the bulk of said data, the second one of said at least two sections having a disparately small number of shift register blocks for storing high priority data, each of said shift register blocks comprising; a plurality of charge coupled shift register bit positions arranged in a series bit stream formed in a semiconductor substrate, and responsive to a source of clock pulses providing a plurality of clock pulses for shifting data bits in a first of two possible directions; first means connected between said source of clock pulses and said plurality of charge coupled shift register bit positions, responsive to said source of clock pulses and also responsive to one of two mutually exclusive shift direction pulses for selectively altering the time of occurrence of said clock pulses, thereby changing the direction of shifting said data bits; bidirectional amplifying means integral with said same semiconductor substrate electrically connected in the series bit stream, for amplifying the data bits; a source of gating pulses; second means connected between said source of gating pulses and said bidirectional amplifying means, responsive to said source of gating pulses and also responsive to the same one of said two mutually exclusive shift direction pulses for selectively altering the time occurrence of said gating pulses, thereby amplifying data bits in the same direction as shifted in the series bit stream, independently in each of said at least two sections of operatively interconnected shift reGister blocks.
Claim 7
Dependent Claim
63 words
A bidirectional charge coupled device shift register system as in claim 4 wherein said first means comprises; a plurality of gating circuits responsive to at least two of said plurality of clock pulses and also responsive to the one of two mutually exclusive shift direction pulses for interchanging the time of occurrence of said at least two of said plurality of clock pulses.
Claim 8
Dependent Claim
62 words
A charge coupled device shift register system as in claim 4 wherein said second means comprises; a plurality of gating circuits responsive to at least two of said plurality of gating pulses and also responsive to the one of two mutually exclusive shift direction pulses for interchanging the time of occurrence of said at least two of said plurality of gating pulses.
References Cited (Backward Citations)
US3670313A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |