Electronic digital clock apparatus

Claim 2

An electronic digital clock apparatus comprising: shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number; generating means for generating pulses; an adder means connected to said shift register means to form a closed loop therewith, said adder means including two input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time, said adder means comprising: a two-input EXCLUSIVE OR means including a first input terminal for receiving said outputs from said shift register means and a second input terminal for receiving said addition input; an AND means having two input terminals which are respectively connected to those of said EXCLUSIVE OR means; a delay means for receiving an output from said AND means to produce an output after a predetermined time interval; and an OR gate means for coupling said output from said delay means and said addition input to said second input terminal of said EXCLUSIVE OR means; shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time; a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

Claim 3

An electronic digital clock apparatus comprising: shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number; generating means for generating pulses; an adder means connected to said shift register means to form a closed loop therewith, said adder means including two input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time; shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time; detector means connected to a predetermined stage of said shift register means for detecting whether outputs from said stage correspond to a predetermined number, said detector means producing an output when said outputs correspond to said predetermined number; reset gate means connected to the output side of said predetermined stage within said closed loop for resetting successive outputs from said predetermined stage in response to said output from said detector means; an AND gate means for coupling said output from said detector means and said addition input to said second input terminal of said adder means; a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

Claim 4

An electronic digital clock apparatus comprising: shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number; generating means for generating pulses; an adder means connected to said shift register means to form a closed loop therewith, said adder means including two input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time; shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time; detector means connected to a predetermined stage of said shift register means for detecting whether outputs from said stage correspond to a predetermined number, said detector means producing an output when said outputs correspond to said predetermined number; reset gate means connected to the output side of said predetermined stage within said closed loop for resetting successive outputs from said predetermined stage in response to said output from said detector means; an AND gate means for coupling said output from said detector means and said addition input to said second input terminal of said adder means; a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

Claim 5

A clock apparatus according to claim 2 wherein said detector means includes means for holding said detection output for a predetermined time interval.

Claim 6

An electronic digital clock apparatus comprising: shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number; generating means for generating pulses; an adder means connected to said shift register means to form a closed loop therewith, said adder means including tWo input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time; shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time; selector means for selecting the use of said clock apparatus either as a 12-hour or as a 24 hour system; detector means connected to outputs of two adjacent stages of said shift register means for detecting whether numerical information stored in said two stages of said shift register means corresponds to a number 12 or 24 in response to selection by means of said selector means, said detector means producing an output where the numerical information stored in said two adjacent stages corresponds to the number 12 or 24; first and second reset gate means connected to the respective output sides of said two stages of said shift register means within said closed loop resetting successive outputs from each of said two adjacent stages of said shift register means in response to said detection output from said detector means; a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

Claim 7

An electronic digital clock apparatus comprising: shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number; generating means for generating pulses; an adder means connected to said shift register means to form a closed loop therewith, said adder means including tWo input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time; shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time; selector means for selecting the use of said clock apparatus either as a 12-hour or as a 24 hour system; detector means connected to outputs of two adjacent stages of said shift register means for detecting whether numerical information stored in said two stages of said shift register means corresponds to a number 12 or 24 in response to selection by means of said selector means, said detector means producing an output where the numerical information stored in said two adjacent stages corresponds to the number 12 or 24; first and second reset gate means connected to the respective output sides of said two stages of said shift register means within said closed loop resetting successive outputs from each of said two adjacent stages of said shift register means in response to said detection output from said detector means; a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

Claim 8

A clock apparatus according to claim 4 wherein said detector means includes means for holding its output for a predetermined time interval.

Claim 9

A clock apparatus according to claim 4 wherein said adder means comprises two-input EXCLUSIVE OR means including a first input terminal for receiving said outputs from said shift register means and a second input terminal for receiving said addition input; an AND means having two input terminals which are respectively connected to those of said EXCLUSIVE OR means; a delay means for receiving an output from said AND means to produce an output after a predetermined time interval; and an OR gate means for sending said output from said delay means and said addition input to said second input terminal of said EXCLUSIVE OR means.

Claim 10

A clock apparatus according to claim 2 wherein said adder means comprises two-input EXCLUSIVE OR means including a first input terminal for receiving said outputs from said shift register means and a second input terminal for receiving said addition input; an AND means having two input terminals which are respectively connected to those of said EXCLUSIVE OR means a delay means for receiving an output from said AND means to produce an output after a predetermined time interval; and an OR gate means for sending said output from said delay means and said addition input to said second input terminal of said EXCLUSIVE OR means.

Claim 11

A clock apparatus according to claim 1 further comprising: detector means connected to a predetermined stage of said shift register means for detecting whether outputs from said stage correspond to a predetermined number, said detector means producing an output when said outputs correspond to said predetermined number reset gate means connected to the output side of said predetermined stage within said closed loop for resetting successive outputs from said predetermined stage in response to said output from said detector means; and an AND gate means for coupling said output from said detector means and said addition input to said second input terminal of said adder means.

Claim 12

A clock apparatus according to claim 2 wherein said predetermined number is 6.

Claim 13

A clock apparatus according to claim 2 whErein said predetermined number is 10.

Claim 14

A clock apparatus according to claim 8 wherein said detector means includes means for holding said detection output for a predetermined time interval.

Claim 15

A clock apparatus according to claim 1 further comprising: selector means for selecting the use of said clock apparatus either as a 12-hour or as a 24-hour system; detector means connected to outputs of two adjacent stages of said shift register means for detecting whether numerical information stored in said two stages of said shift register means corresponds to a number 12 or 24 in response to selection by means of said selector means, said detector means producing an output where the numerical information stored in said two adjacent stages corresponds to the number 12 or 24; and first and second reset gate means connected to the respective output sides of said two stages of said shift register means within said closed loop for resetting successive outputs from each of said two adjacent stages of said shift register means in response to said detection output from said detector means.

Claim 16

A clock apparatus according to claim 12 wherein said detector means includes means for holding its output for a predetermined time interval.

Claim 17

A clock apparatus according to claim 1 wherein said shift register means is of dynamic type.

Claim 18

A clock apparatus according to claim 1 wherein each stage of said shift register means includes four register elements.