Time slot number compensating arrangement

Claim 2

In a time division switching system having a plurality of port circuits and including clock means for defining a repetitive sequence of time slots, each of said port circuits having a recirculating shift register for carrying a bit designating the assignment of the port circuit to a particular time slot, the combination comprising means for counting said time slots, gating means operable to insert a bit in said shift register of a designated one of said port circuits subsequent to said counting means indicating a particular time slot number, central control means for designating a particular time slot number for assignment to said one of said port circuits and for thereafter interrogating said one of said port circuits to ascertain the time slot number of said bit inserted therein, register means interposed between said central control means and said counting means, and means for decrementing said register incident to said interrogating of said port circuit by said central control means.

Claim 3

In a time division switching system having a plurality of port circuits to which communications connections may be extending during predetermined time slots, central control means for designating a port circuit and a time slot during which the designated port circuit shall be included in a communications connection, wherein each port circuit includes register means for circulating a bit defining the time slot designated for that port circuit, the combination comprising clock means defining a numbered sequence of time slots each including a clock pulse, decoder means for indicating write and clear commands from said central control, means for applying write and clear commands to said port circuit register means, means for matching a time slot number designated by said central control with a count indicated by said clock means for energizing said applying means to deliver to said central control designated port circuit said command indicated in said decoder means, bus means associated with said plurality of port circuits for exhibiting a signal condition representing the time slot defined by the circulating register means in a designated one of said port circuits, means for registering the time slot number defined by said clock means when said bus means exhibits said signal condition, and means for decrementing said means for registering incident to transmitting the contents of said registering means to said central control means.

Claim 4

In a time division switching system having a plurality of port circuits to which communications connections may be extending during predetermined time slots, central control means for designating a port circuit and a time slot during which the designated port circuit shall be included in a communications connection, wherein each port circuit includes register means for circulating a bit defining the time slot designated for that port circuit, the combination comprising clock means defining a numbered sequence of time slots each including a clock pulse, decoder means for indicating write and clear commands from said central control, means for applying write and clear commands to said port circuit register means, means for matching a time slot number designated by said central control with a count indicated by said clock means for energizing said applying means to deliver to said central control designated port circuit said command indicated in said decoder means, bus means associated with said plurality of port circuits for exhibiting a signal condition representing the time slot defined by the circulating register means in a designated one of said port circuits, means for registering the time slot number defined by said clock means when said bus means exhibits said signal condition, and means for decrementing said means for registering incident to transmitting the contents of said registering means to said central control means.

Claim 5

In a time division switching system according to claim 2, the combination wherein said clock means is connected to apply clock pulses to said circulating register means and wherein said circulating register means is adapted to receive said time slot defining bit upon being supplied with said write command signal prior to the receipt of said clock pulse from said clock means.

Claim 6

In a time division switching system according to claim 3, the combination further including gating means for coupling said registering means to said clock means, and means coupled to said bus means and controlled by said matching means for activating said gating means for entering a time slot number into said registering means.

Claim 7

In a time division switching system having a clock for defining a repetitive sequence of time slots during which communications may be established among a plurality of port circuits, each of said port circuits having a recirculating shift register for carrying a bit designating the assignment of said port circuit to a particular time slot and being adapted to receive said time slot designating bit during one of said time slots following said particular time slot, the combination comprising central control means for accessing and assigning time slot numbers to said port circuits, counter means coupled to said clock for indicating time slot numbers, matching means for matching a count accruing in said counter with a time slot number assigned by said central control means, bus means associated with said plurality of port circuits for exhibiting a signal condition representing the time slot defined by the recirculating register in an accessed one of said port circuits, register means, gate means coupling said counter means to said register means, means coupled to said bus means and controlled by said matching means for activating said gate means to enter a time slot count into said register means, and means for decrementing said register means subsequent to said activating of said gate means.

Claim 8

In a time division switching system having a clock for defining a repetitive sequence of time slots during which communications may be established among a plurality of port circuits, each of said port circuits having a recirculating shift register for carrying a bit designating the assignment of said port circuit to a particular time slot and being adapted to receive said time slot designating bit during one of said time slots following said particular time slot, the combination comprising central control means for accessing and assigning time slot numbers to said port circuits, counter means coupled to said clock for indicating time slot numbers, matching means for matching a count accruing in said counter with a time slot number assigned by said central control means, bus means associated with said plurality of port circuits for exhibiting a signal condition representing the time slot defined by the recirculating register in an accessed one of said port circuits, register means, gate means coupling said counter means to said register means, means coupled to said bus means and controlled by said matching means for activating said gate means to enter a time slot count into said register means, and means for decrementing said register means subsequent to said activating of said gate means.