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US3787628A Expired / Lapsed US ⏱️ 0.0 years remaining

Communication system for the transmission of information between two terminal stations by pulse code modulation

Assignee: US Philips Corp
•
Filing: 1972-01-06
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Granted: 1974-01-22
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Expires: 1992-01-06
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Abstract

Abstract A time division multiplex PCM transmission system in which the coder and decoder present in one and the same terminal station are supervised on conversion accuracy with the interposition of a test signal generator connected to at least one of the incoming channels, a digital store arranged between coder output and decoder input, and a supervision device connected to at least one of the outgoing channels. The digital store is provided with a separate control unit controlling writing and reading of amplitude samples of the test signal converted into a coded form and selecting the consecutive writing and reading intervals in such a manner that they cannot overlap one another in spite of their mutually varying time relation.

Inventors

  • 👤 G Feutsch
  • 👤 G Korevaar
  • 👤 Dijk L Van
  • 👤 J Verhagen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 07:11
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04J; H04J3/00; H04J3/02; H04J3/14

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 403 words
A time division multiplex communication system including two terminal stations connected together through two transmission paths, said stations being substantially identically constituted for transmitting information by pulse code modulation, said stations each having an encoder for information received on incoming channels to be transmitted to the other station, said encoder being coupled to the incoming channels through a time division multiplex device for sequentially providing samples to the encoder representative of the information on the different incoming channels, and a decoder for information received from the other station and to be sent on outgoing channels, said decoder being coupled to the outgoing channels through a time division multiplex device for sequentially providing signals to the respective outgoing channels representative of the decoded information samples received from the other station, said multiplex and demultiplex devices each operative at their own clock frequency, said clock frequency representing a sampling frequency for the incoming and outgoing channels, respectively, said time division multiplex communication system further comprising: A. a signal generator for each station adapted to be connected to at least one of the incoming channels of that respective station; B. supervision means for each station for comparing a received test signal with a reference, for connection to at least one of the outgoing channels of that respective station; C. a digital store for each station, each digital store coupled to the output of said encoder, and the input of said decoder for that respective station; and D. a control unit means for each station for controlling its respective digital store, means associated with each control unit for sensing the respective sampling frequency for said multiplexed incoming channels, means for sensing the sampling frequency for said multiplexed outgoing channels, said control means containing means for writing a sampled signal from said signal generator into its respective store at a frequency which is a submultiple of said sampling frequency of the incoming channels and means for reading the stored signal from said store and applying it to said decoder at a frequency which is substantially equal to said submultiple frequency and in synchronism with the sampling frequency assoicated with the outgoing channels, said control unit further comprising a logic circuit means for delaying readout of said digital store an integral number of frame intervals when a time interval between consecutive writing and reading intervals becomes less than a given minimum duration, whereby overlapping of these intervals is prevented.
Claim 2
Dependent Claim 403 words
A time division multiplex communication system including two terminal stations connected together through two transmission paths, said stations being substantially identically constituted for transmitting information by pulse code modulation, said stations each having an encoder for information received on incoming channels to be transmitted to the other station, said encoder being coupled to the incoming channels through a time division multiplex device for sequentially providing samples to the encoder representative of the information on the different incoming channels, and a decoder for information received from the other station and to be sent on outgoing channels, said decoder being coupled to the outgoing channels through a time division multiplex device for sequentially providing signals to the respective outgoing channels representative of the decoded information samples received from the other station, said multiplex and demultiplex devices each operative at their own clock frequency, said clock frequency representing a sampling frequency for the incoming and outgoing channels, respectively, said time division multiplex communication system further comprising: A. a signal generator for each station adapted to be connected to at least one of the incoming channels of that respective station; B. supervision means for each station for comparing a received test signal with a reference, for connection to at least one of the outgoing channels of that respective station; C. a digital store for each station, each digital store coupled to the output of said encoder, and the input of said decoder for that respective station; and D. a control unit means for each station for controlling its respective digital store, means associated with each control unit for sensing the respective sampling frequency for said multiplexed incoming channels, means for sensing the sampling frequency for said multiplexed outgoing channels, said control means containing means for writing a sampled signal from said signal generator into its respective store at a frequency which is a submultiple of said sampling frequency of the incoming channels and means for reading the stored signal from said store and applying it to said decoder at a frequency which is substantially equal to said submultiple frequency and in synchronism with the sampling frequency assoicated with the outgoing channels, said control unit further comprising a logic circuit means for delaying readout of said digital store an integral number of frame intervals when a time interval between consecutive writing and reading intervals becomes less than a given minimum duration, whereby overlapping of these intervals is prevented.
Claim 3
Dependent Claim 110 words
A system as claimed in claim 1 in which respective clock pulse generators associated with the time division multiplex device and the time division demultiplex device each form part of their own time control device, which respective time control devices supply time slot pulses each subdividing consecutive time division multiplex cycles and time division demultiplex cycles into a plurality of each time slots, one of which is reserved for synchronization, wherein said store is constituted by a shift register, and wherein an amplitude sample of the test signal converted into encoded form is applied to said shift register during each synchronization time slot of the consecutive time division multiplex cycles.
Claim 4
Dependent Claim 86 words
A system as claimed in claim 2, wherein the control unit comprises a first bistable circuit which in dependence upon its instantaneous stable state is set or reset by time slot pulses occurring in a middle of consecutive time division demultiplex cycles to produce a ''''permit'''' signal consisting of pulses which are periodically present and absent and whose duration is equal to the duration of a time division demultiplex cycle, said pulses extending from a middle of one cycle to a middle of a next cycle.
Claim 5
Dependent Claim 175 words
A system as claimed in claim 2, wherein the control unit associated with said shift register further comprises a two-to-one divider to which the synchronization time slot pulses occurring during consecutive time division multiplex cycles are applied, first and second AND gates connected through a common OR gate to a control input of the shift register, said first AND gate being enabled once per two consecutive time division multiplex cycles by output pulses of said two-to-one divider to pass a number of clock pulses required for writing an applied coded value from the clock pulse generator associated with the time division multiplex device, to the control input of said shift register, said second AND gate being enabled once per two consecutive time division demultiplex cycles during a synchronization time slot, and provided that a ''''permit'''' signal is present, is able to pass the number of clock pulses required for reading a stored coded value from said shift register, said clock pulses being derived from the clock pulse generator associated with the time division demultiplex device.
Claim 6
Dependent Claim 161 words
A system as claimed in claim 4, wherein said control unit furthermore comprises a second bistable circuit to which given frame pulses occurring in consecutive time division demultiplex cycles are applied and on the basis of which, said second bistable circuit producing a signal consisting of periodically occurring broad protection pulses whose duration comprises a plurality of time slots, said protection pulses being related to each of the synchronization time slot pulses of the time division demultiplex cycles in a manner, such that each of these synchronization time slot pulses coincide with approximately the middle of a respective protection pulse, and a third AND gate to which said protection pulses and the output pulses provided by said 2-to-1 divider are applied, its output being connected to a reset input of said first bistable circuit, a phase change being introduced into the ''''permit'''' signal provided by said first bistable circuit, when the pulses applied to the third AND gate overlap one another.

References Cited (Backward Citations)

US3057972A Cited
US3154738A Cited
US3496536A Cited
US3683115A Cited
US3622877A Cited
US3691306A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-01-21 1977-07-23 1978-01-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-01-21 1981-07-23 1982-01-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-01-21 1985-07-23 1986-01-22 $7700.00 Window Closed / Lapsed

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