High speed angle gate

Claim 2

In a high speed angle gate circuit, the combination comprising: a. input terminal for receiving a bi-polar directional information pulse whose amplitude is a measure of angular displacement, b. difference amplifier means comprising first and second difference amplifiers coupled to said input terminal for generating an output negative pulse regardless of the polarlity of the input pulse whenever the input pulse amplitude exceeds a predetermined amplitude corresponding to an angular limit, c. pulse adding circuit means having a first input for receiving a negative enabling pulse and a negative input for receiving the negative output pulse from said difference amplifier for cancelling said positive enabling pulse when said negative pulse is generated.

Claim 3

The high speed gate of claim 1 wherein said first difference amplifier has clipping means for clipping positive input pulses and said second difference amplifier has clipping means for clipping negative input pulses.

Claim 4

The high speed gate of claim 1 wherein said difference amplifier means includes: a a first difference amplifier including first and second transistors having a base, collector and emitter, b the base of said first transistor being coupled to said input terminal means, c the collector of said first transistor being connected to a B-voltage supply, d the emitters of said first and second transistors being connected to a B+ voltage supply, e the collector of said second transistor being connected through a load resistor to the B- voltage supply and f a second difference amplifier including third and fouth transistors having a base, collector and emitter, g the base of said third transistor being connected to said input terminal means, h the collector of said third transistor being connected throuGh a load resistor to the B+ voltage supply, i the emitters of said third and fourth transistors being connected to the B- voltage supply, j the collector of said fourth transistor being connected to the B+ voltage supply, k the collector of said second transistor being connected through adding resistors to the collector of said third transistor, l a voltage divider network having a first terminal connected to said B- voltage supply and a second terminal connected to said B+ voltage supply, m the bases said second and fourth transistors being connected to said voltage divider network for providing negative and positive voltages to the bases of said second and fourth transistors representing, respectively, the lower and upper angle limits.