US3786362A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Balanced output operational amplifier
Assignee: AT&T Inc
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Filing: 1972-02-07
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Granted: 1974-01-15
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Expires: 1992-02-07
Abstract
Abstract An operational amplifier which provides a balanced output signal and whose differential input stage utilizes active loads. A common mode signal is derived from the balanced output signal and used via a comparator and a feedback loop to control the operation of the active loads.
Inventors
- 👤 D Marsh
- 👤 T Maxfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:11
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/45484; H03F3/45488; H03F3/45493; H03F3/45511; H03F3/45076; H03F3/4508; H03F3/4517; H03F2203/00; H03F2203/45; H03F2203/45402; H03F2203/45418; H03F2203/45424; H03F2203/45648; H03F2203/45696
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
In a balanced output signal operational amplifier having a differentially connected input stage for receiving applied input signals, said input stage biased by a constant current source and having its output terminals respectively connected to the collector terminals of first and second active load transistors, the base terminals of said first and second transistors connected in common and the emitter terminals of said first and second transistors connected, respectively, by an impedance element to a terminal of fixed potential, the improvement comprising: means responsive to the signals developed at said output terminals of said input stage for supplying a balanced output signal; means responsive to said balanced output signal for developing a signal representative of the arithmetic average of said balanced output signal; means for comparing said representative signal with a predetermined reference signal to develop a control signal; and means for supplying said control signal to the base terminals of said first and second transistors.
Claim 2
Dependent Claim
156 words
In a balanced output signal operational amplifier having a differentially connected input stage for receiving applied input signals, said input stage biased by a constant current source and having its output terminals respectively connected to the collector terminals of first and second active load transistors, the base terminals of said first and second transistors connected in common and the emitter terminals of said first and second transistors connected, respectively, by an impedance element to a terminal of fixed potential, the improvement comprising: means responsive to the signals developed at said output terminals of said input stage for supplying a balanced output signal; means responsive to said balanced output signal for developing a signal representative of the arithmetic average of said balanced output signal; means for comparing said representative signal with a predetermined reference signal to develop a control signal; and means for supplying said control signal to the base terminals of said first and second transistors.
Claim 3
Dependent Claim
222 words
In a balanced output signal operational amplifier having an input stage differentially connected for receiving applied input signals, said input stage biased by a constant current source and having its output terminals respectively connected to the collector terminals of first and second load transistors, the base terminals of said first and second transistors connected in common and the emitter terminals of said first and second transistors connected, respectively, by an impedance element to a terminal of fixed potential, the improvement comprising: means responsive to the signals developed at said input stage output terminals for supplying a balanced output signal; means responsive to said balanced output signal for developing a signal representative of the arithmetic average of said balanced output signal; third and fourth transistors having their emitter terminals commonly connected to a source of constant current, the collector terminal of said fourth transistor connected to said terminal of fixed potential, the base terminal of said fourth transistor supplied with a predetermined reference signal; a fifth transistor having its base and collector terminals commonly connected to the collector terminals of said third transistor and the base terminals of said first and second transistors, the emitter terminal of said fifth transistor connected to said terminal of fixed potential; and means for supplying said representative average signal to the base terminal of said third transistor.
Claim 4
Dependent Claim
222 words
In a balanced output signal operational amplifier having an input stage differentially connected for receiving applied input signals, said input stage biased by a constant current source and having its output terminals respectively connected to the collector terminals of first and second load transistors, the base terminals of said first and second transistors connected in common and the emitter terminals of said first and second transistors connected, respectively, by an impedance element to a terminal of fixed potential, the improvement comprising: means responsive to the signals developed at said input stage output terminals for supplying a balanced output signal; means responsive to said balanced output signal for developing a signal representative of the arithmetic average of said balanced output signal; third and fourth transistors having their emitter terminals commonly connected to a source of constant current, the collector terminal of said fourth transistor connected to said terminal of fixed potential, the base terminal of said fourth transistor supplied with a predetermined reference signal; a fifth transistor having its base and collector terminals commonly connected to the collector terminals of said third transistor and the base terminals of said first and second transistors, the emitter terminal of said fifth transistor connected to said terminal of fixed potential; and means for supplying said representative average signal to the base terminal of said third transistor.
Claim 5
Dependent Claim
258 words
In a balanced output signal amplifier having first and second input transistors differentially connected for receiving input signals applied to the base terminals of said transistors, the emitter terminals of said transistors connected in common to a first source of fixed potential by a first constant current source, the collector terminals of said transistors respectively connected to the collector terminals of third and fourth transistors, the base terminals of said third and fourth transistors connected in common, and the emitter terminals of said third and fourth transistors connected, respectively, by a resistive element to a second source of fixed potential, the improvement comprising: means responsive to the signals developed at said first and second transistor collector terminals for supplying a balanced output signal; means responsive to said balanced output signal for developing a signal representative of the arithmetic average of said balanced output signal; fifth and sixth transistors having their emitter terminals commonly connected by a second constant current source to said first source of fixed potential, the collector terminal of said sixth transistor connected to said second source of fixed potential and the base terminal of said sixth transistor connected to a source of reference potential; a seventh transistor having its base and collector terminals commonly connected to the collector terminal of said fifth transistor and the common base terminal of said third and fourth transistors, the emitter terminal of said seventh transistor connected to said second source of fixed potential; and means for supplying said representative average signal to the base terminal of said fifth transistor.
Claim 6
Dependent Claim
258 words
In a balanced output signal amplifier having first and second input transistors differentially connected for receiving input signals applied to the base terminals of said transistors, the emitter terminals of said transistors connected in common to a first source of fixed potential by a first constant current source, the collector terminals of said transistors respectively connected to the collector terminals of third and fourth transistors, the base terminals of said third and fourth transistors connected in common, and the emitter terminals of said third and fourth transistors connected, respectively, by a resistive element to a second source of fixed potential, the improvement comprising: means responsive to the signals developed at said first and second transistor collector terminals for supplying a balanced output signal; means responsive to said balanced output signal for developing a signal representative of the arithmetic average of said balanced output signal; fifth and sixth transistors having their emitter terminals commonly connected by a second constant current source to said first source of fixed potential, the collector terminal of said sixth transistor connected to said second source of fixed potential and the base terminal of said sixth transistor connected to a source of reference potential; a seventh transistor having its base and collector terminals commonly connected to the collector terminal of said fifth transistor and the common base terminal of said third and fourth transistors, the emitter terminal of said seventh transistor connected to said second source of fixed potential; and means for supplying said representative average signal to the base terminal of said fifth transistor.
Claim 7
Dependent Claim
251 words
In a differential output signal amplifier having first and second input transistors differentially connected for receiving input signals applied to the base terminals of said transistors, the emitter terminals of said transistors connected in common to a first source of fixed potential by a constant current source, the collector terminals of said transistors respectively connected to the collector terminals of third and fourth transistors, the base terminals of said third and fourth transistors connected in common, and the emitter terminals of said third and fourth transistors connected, respectively, by an impedance element to a second source of fixed potential, the improvement comprising: means responsive to the signals developed at said first and second transistor collector terminals for supplying a differential output signal; means responsive to said differential output signal for developing a signal representative of the arithmetic average of said differential output signal; fifth and sixth transistors having their emitter terminals commonly connected to said first source of fixed potential, the collector terminal of said sixth transistor connected to said second source of fixed potential and the base terminal of said sixth transistor connected to a source of reference potential; a seventh transistor having its base and collector terminals commonly connected to the collector terminal of said fifth transistor and the common base terminal of said third and fourth transistors, the emitter terminal of said seventh transistor connected to said second source of fixed potential; and means for supplying said representative average signal to the base terminal of said fifth transistor.
Claim 8
Dependent Claim
251 words
In a differential output signal amplifier having first and second input transistors differentially connected for receiving input signals applied to the base terminals of said transistors, the emitter terminals of said transistors connected in common to a first source of fixed potential by a constant current source, the collector terminals of said transistors respectively connected to the collector terminals of third and fourth transistors, the base terminals of said third and fourth transistors connected in common, and the emitter terminals of said third and fourth transistors connected, respectively, by an impedance element to a second source of fixed potential, the improvement comprising: means responsive to the signals developed at said first and second transistor collector terminals for supplying a differential output signal; means responsive to said differential output signal for developing a signal representative of the arithmetic average of said differential output signal; fifth and sixth transistors having their emitter terminals commonly connected to said first source of fixed potential, the collector terminal of said sixth transistor connected to said second source of fixed potential and the base terminal of said sixth transistor connected to a source of reference potential; a seventh transistor having its base and collector terminals commonly connected to the collector terminal of said fifth transistor and the common base terminal of said third and fourth transistors, the emitter terminal of said seventh transistor connected to said second source of fixed potential; and means for supplying said representative average signal to the base terminal of said fifth transistor.
References Cited (Backward Citations)
US3275945A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |