Digital regulating control for servo system

Claim 2

In a servo system having a motor for driving a controlled member in response to an error signal, and a resolver connected with said controlled member for producing a signal responsive to the movement thereof, the combination comprising; a first counter connected to a source of clock pulses for counting said clock pulses, a second counter connected to a source of command pulses for counting said command pulses, a comparator connected with said first and second counters for producing a signal having a frequency proportional to the difference in the frequency between said clock pulses and said command pulses, means for comparing the phase of said comparator-produced signal with said revolverproduced signal for producing said error signal in response to the difference in phase therebetween.

Claim 3

Apparatus according to claim 1 wherein said phase comparator means comprises gate means connected with said resolver and with said comparator for producing a train of pulses, each of said pulses having a duration proportional to the difference in phase between said resolver-produced signal and said comparator-produced signal, and means for integrating said pulse train to produce an error signal having a level proportional to the duration of each of said pulses.

Claim 4

Apparatus according to claim 2 including first and second amplifier units, said first amplifier units being connected directly with said gate means for receiving said pulse train, inverter means, said second amplifier unit being connected to said gate means through said inverter means for receiving said pulse train in inverted form, means connected with said first and second amplifier units for producing an average pulse train having an instantaneous amplitude equal to the average values of the outputs of said amplifier units, and means for selectively maintaining the input of one of said amplifier units at a constant level.

Claim 5

Apparatus according to claim 3 wherein said last named means comprises a bistable device having a setting input, a clock input, and two mutually exclusive outputs, said bistable device having its setting input connected with said resolver and its clock input connected with said comparator. An exclusively-OR gate having its two inputs connected individually with said comparator and with said resolver, said gate means comprising first and second control gates each having first input connected in common to the output of said exclusive-OR gate and its other input connected individually to the two mutually exclusive outputs of said bistable device, one of said control gates being connected directly to said first amplifier unit, and inverter means for connecting said control gates to said second amplifier unit.

Claim 6

Apparatus according to claim 1 including dividing means connected to said resolver for dividing the frequency of said resolver-produced signal, and dividing means connected to said comparator for dividing the frequency of said comparator-produced signal, both of said dividing means having the same radix.

Claim 7

Apparatus according to claim 1 including means connected with said first counter for deriving a two-phase a.c. signal from said clock pulses, said a.c. signal having a frequency equal to an integral submultiple of the frequency of said clock pulses, and means for connecting said two-phase a.c. signal to said resolver.

Claim 8

Apparatus according to claim 1 including means for deriving a control pulse train from said first counter, said control pulse train having a frequency equal to a submultiple of the frequency of said clock pulses, connecting means for selective applying said control pulse train to said second counter to advance the state thereof, and means responsive to a predetermined relation between the phase of said comparator-generated signal and said resolver-generated signal for terminating the advancement of said second counter by said control pulse train.

Claim 9

Apparatus according to claim 7 including control means connected with said comparator and with said resolver, and responsive thereto for disabling said connecting means in response to initiation of a condition in which the phase of said resolver-produced signal is equal to that of said comparator-produced signal.

Claim 10

Apparatus according to claim 8 wherein said control means comprises a monostable multivibrator for producing a short duration pulse during each cycle of said comparator-produced signal, a monostable multivibrator having a pair of mutually exclusive outputs for producing signals indicative of the state of the multivibrator, first and second bistable devices each having a setting input, a clock input, and at least one output for producing a signal indicative of the state of the device, means for connecting one output of said monostable multivibrator with the clock input of said first bistable device, means for connecting the other output of said monostable multivibrator with the clock input of said second bistable device, whereby said first bistable device is enabled to be set at the beginning of the quasi-stable state of said multivibrator and said second bistable device is enabled to be set at the end of said quasi-stable state, and means for connecting said resolver-produced signal directly to the setting input of said first bistable device, inverter means for connectIng said resolver-produced signal to the setting input of said second bistable device, gate means connected with the outputs of said first and second bistable devices for producing a coincidence signal when both of said flip-flops are simultaneously in their set state, and means responsive to said gate means for selectively applying said control pulse train to said second counter until said gate means produces said coincidence signal.

Claim 11

Apparatus according to claim 8 including means for selectively disabling said control means.