Abstract A method for fabricating a semiconductor device which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a <100> plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the <100> oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a <100> plane with a plurality of semiconductor devices within the substrate is described. The devices may be isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less then approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.
The method of fabricating a monolithic integrated circuit structure comprising: providing a monocrystalline silicon semiconductor substrate having a surface crystallographic orientation parallel to the <100> plane; forming an insulator layer over the surface which results in a density of interface states at the insulator layer to semiconductor interface of less than approximately 2 X 1013 per cm2; forming a plurality of PN junctions wherein the N regions are formed by an open tube diffusion process with the phosphorus source concentration being between about 2.5 X 103 ppm and 4.0 X 103 ppm, said junctions being passivated by said insulation layer; and electrically connecting the devices formed at least in part by said PN junctions to produce desired circuits.
Claim 2
Dependent Claim
20 words
The method of claim 2 wherein the circuit area density is greater than about one circuit per 200 square mils.
Claim 3
Dependent Claim
38 words
The method of claim 3 wherein after said providing step, an epitaxial layer is grown on said substrate having a surface crystallographic orientation parallel to the <100> plane from the said sUbstrate and substantially perpendicular to said substrate.
Claim 4
Independent Claim
190 words
The method of fabricating a monolithic integrated circuit device comprising: providing a monocrystalline silicon semiconductor substrate of one conductivity having a plurality of regions therein of another conductivity; said substrate having a surface crystallographic orientation parallel to the <100> plane; growing an epitaxial layer of said other conductivity having a surface crystallographic orientation parallel to the <100> plane from the said substrate and substantially perpendicular to said substrate; said regions diffusing into said layer and extending in all directions in said substrate by diffusion during the growth of said layer; forming an insulator layer over the surface of said layer which results in a density of interface states at the insulator layer to epitaxial semiconductor layer interface of less than approximately 2 X 1013 per cm2; forming PN isolation regions surrounding said regions in said substrate and extending through said layer to said substrate with a tolerance between the isolation region and said regions of less than 0.3 mils, and being sufficient to avoid electrical shorting therebetween; the circuit area density being greater than one circuit per 200 square mils; and forming semiconductor devices over said regions in said substrate.
Claim 5
Dependent Claim
36 words
The method of claim 5 wherein after the forming of said semiconductor devices, gold is diffused into said devices as an impurity to limit minority carrier lifetime and to improve the gain of the said devices.