All-pass phase-shift circuit

Claim 2

An all-pass phase-shift circuit comprising: a common terminal, an input circuit having first, second, and third terminals for supplying phase reversed signals to the second and third terminals corresponding to an input signal applied between the first terminal and the common terminal, a first capacitor and a first resistor connected in series between the second and third terminals, a second resistor connected in series between the first capacitor and the first resistor, a series connection of a third resistor and a second capacitor connected in parallel with the first resistor, a third capacitor connected in parallel with the second resistor, and means for deriving a phase shifted signal from between the junction of the first and second resistors and the common terminal.

Claim 3

An all-pass phase-shift circuit comprising: a common terminal, an input circuit having first, second, and third terminals for supplying phase reversed signals to the second and third terminals corresponding to an input signal applied between the first terminal and the common terminal, the input circuit including a transistor having its base, collector and emitter electrodes connected to the first, second and third terminals, respectively, a first capacitor and a first resistor connected in series between the second and third terminals, a second resistor connected in series between the first capacitor and the first resistor, a series connection of a third resistor and a second capacitor connected in parallel with the first resistor, a third capacitor connected in parallel with the second resistor, and means for deriving a phase shifted signal from between the junction of the first and second resistors and the common terminal.

Claim 4

An all-pass phase-shift circuit comprising: a common terminal, an input circuit having first, second, and third terminals for supplying phase reversed signals to the second and third terminals corresponding to an input signal applied between the first terminal and the common terminal, the input circuit including a transistor having its base, collector and emitter electrodes connected to the first, second and third terminals, respectively, a first capacitor and a first resistor connected in series between the second and third terminals, a second resistor connected in series between the first capacitor and the first resistor, a series connection of a third resistor and a second capacitor connected in parallel with the first resistor, a third capacitor connected in parallel with the second resistor, and means for deriving a phase shifted signal from between the junction of the first and second resistors and the common terminal.

Claim 5

An all-pass phase-shift circuit as recited in claim 2 wherein the means for deriving an output signal includes an output transistor having base, collector and emitter electrodes, the base electrode being connected to the connection point between the third capacitor and the third resistor, the output signal being derived between the collector and emitter electrodes of the output transistor, and a parallel circuit of a fourth capacitor and a fourth resistor connected between the base electrode of the output transistor and the common terminal.

Claim 6

An all-pass phase-shift circuit as claimed in claim 3 in which at least the input and output transistors are formed on a semiconductor substrate as an IC chip.

Claim 7

An all-pass phase-shift circuit comprising: a. an input transistor having base, collector and emitter electrodes, b. an input circuit connected to the base electrode of the input transistor, c. first and second output transistors each having base, collector and emitter electrodes, d. a common terminal, e. a first RC network connected between the input transistor and the first output transistor and having a first capacitor and a first resistor which are connected in series between the collector and emitter electrodes of the input transistor, a second resistor connected in series between the first capacitor and the first resistor, a series connection of a third resistor and a second capacitor connected in parallel with the first resistor, a third capacitor connected in parallel with the second resistor, the connection point between the third capacitor and the third resistor being connected to the base electrode of the first output transistor, a first output signal being derived from between the common terminal and at least one of the collector and emitter electrodes of the first output transistor, f. a first parallel circuit of a fourth capacitor and a fourth resistor connected between the base electrode of the first output transistor and the common terminal, g. a second RC network connected between the input transistor and the second output transistor and having a fifth capacitor and a fifth resistor connected in series between the collector and emitter electrodes of the input transistor, a sixth resistor connected in series between the fifth capacitor and the fifth resistor, a series connection of a seventh resistor and a sixth capacitor connected in parallel with the fifth resistor, a seventh capacitor connected in parallel with the sixth resistor, the connection point between the seventh capacitor and the seventh resistor being connected to the base electrode of the second output transistor, each element of the second RC network having different values from each corresponding element of the first RC network, a second output signal being derived from between at least one of the collector and emitter electrodes of the second output transistor and the common terminal, and h. a second parallel circuit of an eighth capacitor and an eighth resistor connected between the base electrode of the second output transistor and the common terminal.

Claim 8

An all-pass phase-shift circuit comprising: a. an input transistor having base, collector and emitter electrodes, b. an input circuit connected to the base electrode of the input transistor, c. first and second output transistors each having base, collector and emitter electrodes, d. a common terminal, e. a first RC network connected between the input transistor and the first output transistor and having a first capacitor and a first resistor which are connected in series between the collector and emitter electrodes of the input transistor, a second resistor connected in series between the first capacitor and the first resistor, a series connection of a third resistor and a second capacitor connected in parallel with the first resistor, a third capacitor connected in parallel with the second resistor, the connection point between the third capacitor and the third resistor being connected to the base electrode of the first output transistor, a first output signal being derived from between the common terminal and at least one of the collector and emitter electrodes of the first output transistor, f. a first parallel circuit of a fourth capacitor and a fourth resistor connected between the base electrode of the first output transistor and the common terminal, g. a second RC network connected between the input transistor and the second output transistor and having a fifth capacitor and a fifth resistor connected in series between the collector and emitter electrodes of the input transistor, a sixth resistor connected in series between the fifth capacitor and the fifth resistor, a series connection of a seventh resistor and a sixth capacitor connected in parallel with the fifth resistor, a seventh capacitor connected in parallel with the sixth resistor, the connection point between the seventh capacitor and the seventh resistor being connected to the base electrode of the second output transistor, each element of the second RC network having different values from each corresponding element of the first RC network, a second output signal being derived from between at least one of the collector and emitter electrodes of the second output transistor and the common terminal, and h. a second parallel circuit of an eighth capacitor and an eighth resistor connected between the base electrode of the second output transistor and the common terminal.

Claim 9

An all-pass phase-shift circuit as recited in claim 5 in which the input transistor and the first and second output transistors are formed on the same semiconductor substrate as an IC chip.

Claim 10

An all-pass phase shift circuit as recited in claim 5 in which the resistance values of the fifth, sixth and seventh resistors and the capacitance values of the fifth, sixth and seventh capacitors are selected to be substantially twice those of the first, second and third resistors and those of the first, second and third capacitors, respectively.

Claim 11

An all-pass phase-shift circuit comprising: a. an input circuit having an input terminal and first and second output terminals and delivering to the first and second output terminals signals representative of a signal applied to the input terminal but which are opposite in phase with respect to each other, b. a first capacitor group of n number of capacitors (where n is a positive integer greater than 3) connected in series with the first capacitor of the first group of capacitors being connected to the first output terminal, c. a second capacitor group of n-1 number of capacitors connected in series with the first capacitor of the second group of capacitors being connected to the second output terminal, d. a series circuit of a first and a second resistor connected in series between the connection point of the first and second capacitors of the first capacitor group and the connection point of first and second capacitors of the second capaCitor group, e. a plurality of resistor groups, each group being connected between the connection points of the corresponding remaining adjacent pairs of capacitors of the first and second capacitor groups, each of the resistor groups having two resistors connected in series, f. a third resistor connecting the nth capacitor of the first capacitor group to the (n-1)th capacitor of the second capacitor group, the g. first connecting means for connecting the connection point between the first and second resistors of each of the resistor groups, the connection point between the first and second resistors, and one end of the third resistor the phase-shifted output signal being derived from between the one end of the third resistor and the common terminal.

Claim 12

An all-pass phase-shift circuit comprising: a. an input circuit having an input terminal and first and second output terminals and delivering to the first and second output terminals signals representative of a signal applied to the input terminal but which are opposite in phase with respect to each other, b. a first capacitor group of n number of capacitors (where n is a positive integer greater than 3) connected in series with the first capacitor of the first group of capacitors being connected to the first output terminal, c. a second capacitor group of n-1 number of capacitors connected in series with the first capacitor of the second group of capacitors being connected to the second output terminal, d. a series circuit of a first and a second resistor connected in series between the connection point of the first and second capacitors of the first capacitor group and the connection point of first and second capacitors of the second capaCitor group, e. a plurality of resistor groups, each group being connected between the connection points of the corresponding remaining adjacent pairs of capacitors of the first and second capacitor groups, each of the resistor groups having two resistors connected in series, f. a third resistor connecting the nth capacitor of the first capacitor group to the (n-1)th capacitor of the second capacitor group, the g. first connecting means for connecting the connection point between the first and second resistors of each of the resistor groups, the connection point between the first and second resistors, and one end of the third resistor the phase-shifted output signal being derived from between the one end of the third resistor and the common terminal.