US3783228A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing integrated circuits
Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1970-12-28
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Granted: 1974-01-01
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Expires: 1990-12-28
Abstract
Abstract In the manufacture of a pattern of an integrated circuit, a reference mark is detected by an electron beam scan to correctly determine the position of the pattern on each semiconductor chip, or to correctly combine the patterns of circuit elements. The reference mark may also be used to locate defects of the semiconductor material so as to avoid defective regions.
Inventors
- 👤 Y Tarui
- 👤 S Denda
- 👤 H Baba
- 👤 Y Komimiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:55
CPC Classifications
H; H01; H01J; H01J37/00; H01J37/30; H01J37/304; H01J37/3045; H10; H10P; H10P95/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
175 words
A method of manufacturing a circuit pattern from a semiconductor wafer, said method comprising the steps of: storing information in a computer means, the information being representative of a circuit pattern as well as a positional reference point therefor, which positional reference point is to be correlated with the position of a reference mark formed on the semiconductor wafer; forming a referance mark at a predetermined position on the semiconductor wafer, the reference mark being defined by an isolated p-n junction; scanning the surface of the semiconductor wafer with an electron beam such that the electron beam scans the p-n junction and the adjacent surface area of the wafer; detecting the result of the scanning so as to locate the position of the p-n junction on the semiconductor wafer and determine the relative position between the electron beam and the reference mark defined by the p-n junction; and forming the circuit pattern on the semiconductor wafer with the electron beam in accordance with the stored pattern information and the detected position of the reference mark.
Claim 2
Independent Claim
175 words
A method of manufacturing a circuit pattern from a semiconductor wafer, said method comprising the steps of: storing information in a computer means, the information being representative of a circuit pattern as well as a positional reference point therefor, which positional reference point is to be correlated with the position of a reference mark formed on the semiconductor wafer; forming a referance mark at a predetermined position on the semiconductor wafer, the reference mark being defined by an isolated p-n junction; scanning the surface of the semiconductor wafer with an electron beam such that the electron beam scans the p-n junction and the adjacent surface area of the wafer; detecting the result of the scanning so as to locate the position of the p-n junction on the semiconductor wafer and determine the relative position between the electron beam and the reference mark defined by the p-n junction; and forming the circuit pattern on the semiconductor wafer with the electron beam in accordance with the stored pattern information and the detected position of the reference mark.
Claim 3
Dependent Claim
57 words
The method as defined in claim 1, wherein the step of scanning the surface of the semiconductor wafer with an electron beam creates secondary electrons having different path lengths at the p-n junction, and wherein the position of the p-n junction on the semiconductor wafer is determined by detecting the difference in the secondary electron path lengths.
Claim 4
Dependent Claim
62 words
The method as defined in claim 2, further including the step of illuminating the reference mark with light prior to the step of scanning the surface of the semiconductor wafer with an electron beam, the illumination generating a photo-electromotive force across the p-n junction enhancing the difference between the path lengths of the secondary electrons at the region of the p-n junction.
Claim 5
Dependent Claim
18 words
The method as defined in claim 3, wherein the light is intensity-modulated by means of a sinusoidal wave.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-31 | 1977-07-02 | 1978-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-31 | 1981-07-02 | 1982-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-31 | 1985-07-02 | 1986-01-01 | $7700.00 | Window Closed / Lapsed |