US3783187A
Expired / Lapsed
US
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Facsimile transmission system
Assignee: Hitachi Ltd
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Filing: 1972-05-05
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Granted: 1974-01-01
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Expires: 1992-05-05
Abstract
Abstract A facisimile transmission system wherein each of white or black run lengths of an original picture is coded into a binary form, whose bit number is required to represent the maximum run length of said original picture, and each of the codes constituted by said number of bits is divided into blocks, each thereof containing a predetermined number of bits, and a bit for discriminating whether the code represents a white or black run length is added to the block containing a first ''''1'''' bit starting from the highest order block and is also added to the succeeding block or blocks, thereby eliminating the block or blocks, which precede said block containing the first ''''1'''' bit and contain only ''''0'''' bits to constitute only insignificant portions, so as to reduce the number of bits of the codes to be transmitted and to thereby compress a bandwidth of a facsimile signal. Typically, the number of bits of a run length is less than ten, but not necessarily.
Inventors
- 👤 T Kusama
- 👤 T Hyodo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:35
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/41; H04N1/411; H04N1/413; H04N1/419
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
116 words
A method of compressing the bandwidth in facsimile transmission, comprising the steps of: converting the lengths of each black and white level portion of a binary signal into respective binary codes of 0 and 1 digits having predetermined code lengths, dividing the coded signal into a plurality of blocks of equal length, and adding a bit distinguishing between the white level and black level portions of the binary siGnal to the block in which digit 1 first appears successively from the most significant digit, and to the following blocks of that particular level, while omitting all the blocks preceeding the block of that level containing said first appearing digit 1, thereby reducing the required code length.
Claim 2
Independent Claim
116 words
A method of compressing the bandwidth in facsimile transmission, comprising the steps of: converting the lengths of each black and white level portion of a binary signal into respective binary codes of 0 and 1 digits having predetermined code lengths, dividing the coded signal into a plurality of blocks of equal length, and adding a bit distinguishing between the white level and black level portions of the binary siGnal to the block in which digit 1 first appears successively from the most significant digit, and to the following blocks of that particular level, while omitting all the blocks preceeding the block of that level containing said first appearing digit 1, thereby reducing the required code length.
Claim 3
Dependent Claim
31 words
A method according to claim 1, wherein the coded facsimile signal is temporarily stored in a memory before said coded signal is subjected to the steps of dividing, adding and omitting.
Claim 4
Dependent Claim
97 words
A method according to claim 1, wherein the coded facsimile signal is temporarily stored in a memory prior to the steps of dividing, adding and omitting, and the quantity of information stored in said memory is monitored at all times, whereby the codes that are different from the codes carrying information are sent forth when there is no information in said memory in order that the rate of transmission of the information may be varied correspondingly within the maximum allowable rate determined by the characteristics of the transmission line to reduce the required capacity of said memory.
Claim 5
Independent Claim
184 words
An apparatus for compressing the bandwidth in a facsimile transmission system employing binary coded data signals representing the black and white levels of a video signal comprising: first means, responsive to said binary-coded data signal, for converting the lengths of the black and white level portions thereof into binary codes of 0 and 1 digits having predetermined code lengths; second means, responsive to said first means, for dividing the coded signal into a plurality of blocks of equal length; third means, responsive to said first means and said second means, for generating for each of said blocks an additional bit, which represents one of said white and black level portions of the binary data signal; fourth means, responsive to said second and third means, for adding said respective additional bit to the block, in which digit 1 first appears successively from the most significant digit, and to the following blocks of that particular level; and fifth means, responsive to said first means, for omitting all blocks preceeding the block of that level containing said first appearing digit 1, thereby reducing the required code length.
Claim 6
Independent Claim
184 words
An apparatus for compressing the bandwidth in a facsimile transmission system employing binary coded data signals representing the black and white levels of a video signal comprising: first means, responsive to said binary-coded data signal, for converting the lengths of the black and white level portions thereof into binary codes of 0 and 1 digits having predetermined code lengths; second means, responsive to said first means, for dividing the coded signal into a plurality of blocks of equal length; third means, responsive to said first means and said second means, for generating for each of said blocks an additional bit, which represents one of said white and black level portions of the binary data signal; fourth means, responsive to said second and third means, for adding said respective additional bit to the block, in which digit 1 first appears successively from the most significant digit, and to the following blocks of that particular level; and fifth means, responsive to said first means, for omitting all blocks preceeding the block of that level containing said first appearing digit 1, thereby reducing the required code length.
Claim 7
Dependent Claim
48 words
An apparatus according to claim 4, wherein said first means comprises a source of clock pulses, means, responsive to said source of clock pulses, for counting said clock pulses, and means, responsive to said data signal, for controlling the counting of said clock pulses by said counting means.
Claim 8
Dependent Claim
82 words
An apparatus according to claim 5, wherein said controlling means comprises a timing means, receiving said data signals, for generating timing pulses at the rise and fall times of said data signal, a first delay circuit, responsive to said timing pulse generator means, for providing a first read-out pulse and a second delay circuit, responsive to said first read-out pulse generated by said first delay circuit, for generating a second read-out pulse and supplying said second readout pulse to said counting means.
Claim 9
Dependent Claim
42 words
An apparatus according to claim 6, wherein said counting means comprises a plurality of counting circuits, connected in cascaded groups, each of which receives said second read-out pulse and the first of which is connected directly to said source of clock pulses.
Claim 10
Dependent Claim
78 words
An apparatus according to claim 7, wherein said second means comprises a plurality of first gate circuits, corresponding to said plurality of blocks and a cascaded group of counting circuits associated therewith, wherein each first gate circuit has an input thereof connected to the output of each counting circuit in its corresponding group and wherein the output of each first gate circuit is connected to an input of first registers associated with an adjacent group of counting circuits.
Claim 11
Dependent Claim
74 words
An apparatus according to claim 8, wherein said thrid means comprises a plurality of second gate circuits, corresponding to said plurality oF blocks, one input of each of which is respectively connected to receive said binary data signal, a second input of each of which is connected to the outputs of the counters corresponding to that block, and another input of each of which is connected to the output of said first delay circuit.
Claim 12
Dependent Claim
59 words
An apparatus according to claim 9, wherein said fifth means includes a plurality of third gate circuits, each of which is associated with a respective group of counting circuits and is responsive to the outputs of each counting circuit in its associated group and has one of its outputs connected to the first gate circuit of that respective group.
Claim 13
Dependent Claim
17 words
An apparatus according to claim 10, further wherein said fourth means includes of said second gate circuits.
Claim 14
Dependent Claim
24 words
An apparatus according to Claim 11, wherein said third gate circuits are ''''OR'''' gates and said first and second gate circuits are ''''AND'''' gates.
Claim 15
Dependent Claim
49 words
An apparatus according to claim 4, further including a memory apparatus connected to temporarily store a facsimile coded signal, a memory control apparatus connected thereto for generating dummy codes in said memory when no information exists in said memory and a modulator for modulating the output of said memory.
Claim 16
Dependent Claim
80 words
An apparatus according to claim 13, further including a receiver for demodulating and decoding the output of said modulator comprising a demodulator for demodulating the signal produced by said modulator, a receiver memory apparatus connected thereto, a dummy code detector connected to said demodulator and said receiver memory apparatus for preventing the dummy code from entering said receiver memory, a decoder connected to the output of said receiver memory apparatus and a replica scanning section for producing said decoded signal.
Claim 17
Dependent Claim
49 words
An apparatus according to claim 12, further including a memory apparatus connected to temporarily store a facsimile coded signal, a memory control apparatus connected thereto for generating dummy codes in said memory when no information exists in said memory and a modulator for modulating the output of said memory.
Claim 18
Dependent Claim
80 words
An apparatus according to claim 15, further including a receiver for demodulating and decoding the output of said modulator comprising a demodulator for demodulating the signal produced by said modulator, a receiver memory apparatus connected thereto, a dummy code detector connected to said demodulator and said receiver memory apparatus for preventing the dummy code from entering said receiver memory, a decoder connected to the output of said receiver memory apparatus and a replica scanning section for reproducing said decoded signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-31 | 1977-07-02 | 1978-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-31 | 1981-07-02 | 1982-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-31 | 1985-07-02 | 1986-01-01 | $7700.00 | Window Closed / Lapsed |