US3781877A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Astable multivibrator d.c. bell
Assignee: Edwards Co Inc
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Filing: 1972-04-14
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Granted: 1973-12-25
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Expires: 1992-04-14
Abstract
Abstract A direct current bell is provided having a reciprocating bell striker driven by an astable multivibrator having first and second timing capacitors of different values for providing a 40 percent duty cycle at the natural frequency of the bell striker. A means is provided for protecting the transistors of the multivibrator from excessive reverse bias potentials generated by the timing capacitors.
Inventors
- 👤 C Berns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:42
CPC Classifications
G; G10; G10K; G10K1/00; G10K1/06; G10K1/062; G10K1/063; G10K1/064
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
283 words
An astable multivibrator driven D.C. bell having a housing, a gong supported by the housing and a solenoid actuated striker assembly for striking said gong wherein the improvement comprises: a. an asymmetric free-running multivibrator which generates a frequency comparable to the natural frequency of the striker assembly for periodically actuating said solenoid actuated striker assembly and including: 1. first and second timing means including first and second capacitors, respectively, and wherein said first and second timing means have different timing values effective when activated for controlling the periods of energization and deenergization, respectively, of the solenoid of said solenoid actuated striker assembly so that the period of deenergization is always greater than the period of energization, 2. first and second transistors governed by the timing means for alternately activating the first and second timing means, 3. one terminal of said first and second capacitors of the first and second timing means being connected to the base of the first and second transistors, respectively, through individual diodes and having the other terminal of said first and second capacitors connected to the collectors of the second and first transistors, respectively, and wherein said diodes are poled for protecting said transistors against an excessive reverse bias, and b. driver circuit means including a third transistor which is controlled jointly by the timing means and the first and second transistors for delivering an output to the solenoid during the time interval when the first timing means is active, c. whereby the solenoid is energized for less than 50 percent of the duty cycle time for each actuation of the striker assembly when it is actuated at a frequency comparable to the natural frequeNcy of the striker assembly.
Claim 2
Dependent Claim
283 words
An astable multivibrator driven D.C. bell having a housing, a gong supported by the housing and a solenoid actuated striker assembly for striking said gong wherein the improvement comprises: a. an asymmetric free-running multivibrator which generates a frequency comparable to the natural frequency of the striker assembly for periodically actuating said solenoid actuated striker assembly and including: 1. first and second timing means including first and second capacitors, respectively, and wherein said first and second timing means have different timing values effective when activated for controlling the periods of energization and deenergization, respectively, of the solenoid of said solenoid actuated striker assembly so that the period of deenergization is always greater than the period of energization, 2. first and second transistors governed by the timing means for alternately activating the first and second timing means, 3. one terminal of said first and second capacitors of the first and second timing means being connected to the base of the first and second transistors, respectively, through individual diodes and having the other terminal of said first and second capacitors connected to the collectors of the second and first transistors, respectively, and wherein said diodes are poled for protecting said transistors against an excessive reverse bias, and b. driver circuit means including a third transistor which is controlled jointly by the timing means and the first and second transistors for delivering an output to the solenoid during the time interval when the first timing means is active, c. whereby the solenoid is energized for less than 50 percent of the duty cycle time for each actuation of the striker assembly when it is actuated at a frequency comparable to the natural frequeNcy of the striker assembly.
Claim 3
Dependent Claim
18 words
first and second transistors governed by the timing means for alternately activating the first and second timing means,
Claim 4
Dependent Claim
18 words
first and second transistors governed by the timing means for alternately activating the first and second timing means,
Claim 5
Dependent Claim
35 words
An astable multivibrator driven D.C. bell according to claim 1 wherein the driver circuit means provides an output for a duration that is approximately 40 percent of the duty cycle time of the striker assembly.
Claim 6
Dependent Claim
47 words
An astable multivibrator driven D.C. bell according to claim 1 wherein the multivibrator and driver circuit means are assembled on a printed circuit board which is in turn secured within the housing by a bracket which also serves as a heat sink for the driver circuit means.
Claim 7
Dependent Claim
147 words
one terminal of said first and second capacitors of the first and second timing means being connected to the base of the first and second transistors, respectively, through individual diodes and having the other terminal of said first and second capacitors connected to the collectors of the second and first transistors, respectively, and wherein said diodes are poled for protecting said transistors against an excessive reverse bias, and b. driver circuit means including a third transistor which is controlled jointly by the timing means and the first and second transistors for delivering an output to the solenoid during the time interval when the first timing means is active, c. whereby the solenoid is energized for less than 50 percent of the duty cycle time for each actuation of the striker assembly when it is actuated at a frequency comparable to the natural frequeNcy of the striker assembly.
Claim 8
Dependent Claim
147 words
one terminal of said first and second capacitors of the first and second timing means being connected to the base of the first and second transistors, respectively, through individual diodes and having the other terminal of said first and second capacitors connected to the collectors of the second and first transistors, respectively, and wherein said diodes are poled for protecting said transistors against an excessive reverse bias, and b. driver circuit means including a third transistor which is controlled jointly by the timing means and the first and second transistors for delivering an output to the solenoid during the time interval when the first timing means is active, c. whereby the solenoid is energized for less than 50 percent of the duty cycle time for each actuation of the striker assembly when it is actuated at a frequency comparable to the natural frequeNcy of the striker assembly.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |