Keyboard entry system

Claim 2

A digital timing circuit controlling the input of data from a keyboard to a device accepting key input data comprising: a plurality of bistable elements having in combination at least three mutually exclusive stable states; means responsive to the keyboard for sequencing the bistable elements through at least three of the mutually exclusive states, the sequencing means causing the bistable elements to remain in the sequenced states for controlled periods of time; and means responsive to the sequenced states of the flip flops for generating at least one control signal including a data strobe signal causing the transfer of keyed information to the device accepting key input data.

Claim 3

The circuit as set forth in claim 1 above, wherein the bistable elements include two flip flops having in combination four mutually exclusive states.

Claim 4

The invention as set forth in claim 2 above, wherein the flip flops have the following states in sequential order, 00, 01, 11, 10.

Claim 5

The invention as set forth in claim 3 above, wherein the sequencing means constrains the flip flops to the 00 state unless exactly one key of a selected first group of keys is depressed and sequences the flip flops from the 10 state to the 00 state only when a key of a selected second group of keys is depressed and, in addition only at the conclusion of first and subsequent periods of predetermined length throughout which exactly one key from the first group and one key from the second group has been continuously depressed.

Claim 6

The invention as set forth in claim 4 above, wherein the first period has a duration of approximately 0.4 seconds and the subsequent periods each have a duration of at least 0.05 seconds.

Claim 7

The invention as set forth in claim 3 above, wherein the data strobe signal is generated whenever the flip flops are in the 11 state.

Claim 8

The invention as set forth in claim 1 above, wherein the sequencing means includes a frequency divider circuit having multiple outputs at successively lower frequencies connected to provide timing for the sequencing means.

Claim 9

A keyboard unput system comprising: a keyboard having a plurality of keys, at least one of the keys being an automatic repeat key; means for providing an encoded signal indicative of an activated key in response to the activation of a key; a keyboard logic circuit responsive to the keyboard and generating a one key down signal whenever exactly one key of a selected group of keys is activated and generating a repeat signal whenever a repeat key is depressed; at least two flip flops having in combination a plurality of mutually exclusive stable states; means for sequencing the flip flops through at least three of the mutually exclusive stable states including a first state and a last state in response to the one key down signal, the sequencing means causing the flip flops to remain in sequenced states for predetermined periods of time, constraining the flip flops to the first state in the absence of a one key down signal and seQuencing the flip flops from the last state to the first state only when the repeat signal is being generated; and means responsive to the sequenced states of the flip flops for generating at least one control signal including a data strobe signal causing the transfer of the encoded signal to a device connected to receive key input data, the data strobe signal being generated when the flip flops are in a selected stable state intermediate the first and last states.

Claim 10

A keyboard unput system comprising: a keyboard having a plurality of keys, at least one of the keys being an automatic repeat key; means for providing an encoded signal indicative of an activated key in response to the activation of a key; a keyboard logic circuit responsive to the keyboard and generating a one key down signal whenever exactly one key of a selected group of keys is activated and generating a repeat signal whenever a repeat key is depressed; at least two flip flops having in combination a plurality of mutually exclusive stable states; means for sequencing the flip flops through at least three of the mutually exclusive stable states including a first state and a last state in response to the one key down signal, the sequencing means causing the flip flops to remain in sequenced states for predetermined periods of time, constraining the flip flops to the first state in the absence of a one key down signal and seQuencing the flip flops from the last state to the first state only when the repeat signal is being generated; and means responsive to the sequenced states of the flip flops for generating at least one control signal including a data strobe signal causing the transfer of the encoded signal to a device connected to receive key input data, the data strobe signal being generated when the flip flops are in a selected stable state intermediate the first and last states.

Claim 11

The invention as set forth in claim 8 above, wherein there are two flip flops which are sequenced through four stable states and an additional condition for sequencing of the flip flops from the last stable state to the first stable state is the conclusion of each first and subsequent period of time during which the one key down signal is generated without interruption, the first period being approximately 0.4 second and the subsequent periods being at least 0.05 second.

Claim 12

For use in a key input system having a keyboard having a plurality of keys including a reset key, a return key and a release key; means for providing an encoded signal indicative of a particular activated key in response to the activation of a key; a keyboard logic circuit generating a first signal (ORSTK) in response to activation of the reset key, a second signal (OKDl) in response to activation of exactly one key from a selected group of keys, a third signal (RPTK) in response to activation to a key from a selected second group of keys, a fourth signal (lRETK) in response to non-activation of the return key, a lRELK signal in response to non-activation of a release key, and a fifth signal (OKLOK) signal in response to the presence of a predetermined set of conditions for which the keyboard is to be locked; a high frequency clock signal generator; and a divider circuit generating clock signals at selected submultiples of the high frequency clock signal rate in response to the high frequency clock signal; a timing circuit comprising: a repeat flip flop generating a sixth signal (ORPTF) when in a true state, the repeat flip flop being constrained to a false state in the absence of the OKDl signal and being switched to the true state in response to a simultaneous occurrence of the ORPTK signal and a relatively low frequency clock signal from the divider circuit; first and second flip flops, each having Q and Q outputs representing true and false output states respectively and true, false, clock and clear inputs, the clear inputs being connected to constrain the flip flops to the false output state in response to the absence of the OKDl signal, and the clock inputs being responsive to negative transition of a relatively high frequency clock signal from the divider circuit having a period at least as long as the time required for switch bounce to disappear after activation of a key on the keyboard; means responsive to a true output state of the first flip flop for activating the true input to the second flip flop; means responsive to manual control for generating a FAST REPEAT signal to indicate that automatic repeating should be done at a relatively fast rate; strobe disable logic responsive to the OKLOK, ORSTK, lRETK, and lRELK signals generating a seventh signal (OSTDA) defining the logical function OKLOK + ORSTK . (lRETK + lRELK), input logic responsive to the fast repeat signal, the OSTDA signal and clocking signals from the divider circuit having frequencies of F, F/2, F/4 and F/8, the input logic activating the false input to the second flip flop upon the occurrence of the logical condition F . (FAST REPEAT + F/8) . F/2 . F/4 . ORPTF . QFF2, where QFF2 is the Q output from the second flip flop; means connected to activate the true input to the first flip flop in response to the logical condition QFF2 . F, where QFF2 is the Q output from the second flip flop; means connected to activate the false input to the first flip flop in response to the QFF2 signal; and means responsive to the OSTDA and QFF2 signals and a QFF1 signal representing the Q output of the first flip flop for generating a data strobe signal causing the transfer of keyed information to a device accepting key input data, the data strobe signal being generated upon occurrence of the logical condition QFF1 . QFF2 . OSTDA.

Claim 13

For use in a key input system having a keyboard having a plurality of keys including a reset key, a return key and a release key; means for providing an encoded signal indicative of a particular activated key in response to the activation of a key; a keyboard logic circuit generating a first signal (ORSTK) in response to activation of the reset key, a second signal (OKDl) in response to activation of exactly one key from a selected group of keys, a third signal (RPTK) in response to activation to a key from a selected second group of keys, a fourth signal (lRETK) in response to non-activation of the return key, a lRELK signal in response to non-activation of a release key, and a fifth signal (OKLOK) signal in response to the presence of a predetermined set of conditions for which the keyboard is to be locked; a high frequency clock signal generator; and a divider circuit generating clock signals at selected submultiples of the high frequency clock signal rate in response to the high frequency clock signal; a timing circuit comprising: a repeat flip flop generating a sixth signal (ORPTF) when in a true state, the repeat flip flop being constrained to a false state in the absence of the OKDl signal and being switched to the true state in response to a simultaneous occurrence of the ORPTK signal and a relatively low frequency clock signal from the divider circuit; first and second flip flops, each having Q and Q outputs representing true and false output states respectively and true, false, clock and clear inputs, the clear inputs being connected to constrain the flip flops to the false output state in response to the absence of the OKDl signal, and the clock inputs being responsive to negative transition of a relatively high frequency clock signal from the divider circuit having a period at least as long as the time required for switch bounce to disappear after activation of a key on the keyboard; means responsive to a true output state of the first flip flop for activating the true input to the second flip flop; means responsive to manual control for generating a FAST REPEAT signal to indicate that automatic repeating should be done at a relatively fast rate; strobe disable logic responsive to the OKLOK, ORSTK, lRETK, and lRELK signals generating a seventh signal (OSTDA) defining the logical function OKLOK + ORSTK . (lRETK + lRELK), input logic responsive to the fast repeat signal, the OSTDA signal and clocking signals from the divider circuit having frequencies of F, F/2, F/4 and F/8, the input logic activating the false input to the second flip flop upon the occurrence of the logical condition F . (FAST REPEAT + F/8) . F/2 . F/4 . ORPTF . QFF2, where QFF2 is the Q output from the second flip flop; means connected to activate the true input to the first flip flop in response to the logical condition QFF2 . F, where QFF2 is the Q output from the second flip flop; means connected to activate the false input to the first flip flop in response to the QFF2 signal; and means responsive to the OSTDA and QFF2 signals and a QFF1 signal representing the Q output of the first flip flop for generating a data strobe signal causing the transfer of keyed information to a device accepting key input data, the data strobe signal being generated upon occurrence of the logical condition QFF1 . QFF2 . OSTDA.

Claim 14

The invention as set forth in claim 10 above, wherein the clock signal F has a period of approximately 12.8 milliseconds.

Claim 15

A key input system comprising: a keyboard having a plurality of keys; keyboard logic responsive to the activation of keys on the keyboard, the keyboard logic generating a first signal (OKDl) in response to the activation of exactly one key within a predetermined first group of keys, a second signal (ORPTK) in response to activation of a key within a predetermined second group of keys, and partial address signals uniquely identifying the activation of a key within a predetermined third group of keys; a read only memory providing as an output multibit codes in response to memory locations addressed by the partial address signals and a third signal (OHLFl), a given arrangement of partial address signals defining a word location in a first half of the memory when the OHLFl signal is true and a corresponding word location in a second half of the memory when the OHLFl signal is false; a latch responsive to the output codes from the read only memory and the OHLFl signal, the output codes from the read only memory being latched when the OHLFl signal changes from true to false and being output by the latch so long as the OHLFl signal remains false; at least two flip flops defining in combination at least four mutually exclusive states; means responsive to the ORSTK signal and the OKDl signal for sequencing the flip flops through at least first, second, third and last states respectively, the flip flops being (1) constrained to the first state in the absence of an OKDl signal, (2) sequenced from the first state to the second state only after a sufficient time delay to allow dissipation of keyboard switch bounce, (3) sequenced from the second state to the third state only after sufficient time delay to permit latching of an output code from the first half of the read only memory and establishment of an output from the second half of the read only memory, (4) sequenced from the third state to the last state only after sufficient time to allow the transfer of output codes from the key input system to a data receiving device, and (5) sequenced from the last state to the first state only at the conclusion of each first and subsequent period of time throughout all of which both the OKDl and ORPTK signals remain true, said first period of time being of sufficient duration to allow an operator time to release an activated key under normal keyboard operation circumstances; means responsive to the two flip flops for generating a true OHLFl signal only when the flip flops are in the first state; and means responsive to the flip flops for generating a true data strobe signal to cause transfer of output codes from the latch and the read only memory only when the flip flops are in the third state.

Claim 16

A key input system comprising: a keyboard having a plurality of keys; keyboard logic responsive to the activation of keys on the keyboard, the keyboard logic generating a first signal (OKDl) in response to the activation of exactly one key within a predetermined first group of keys, a second signal (ORPTK) in response to activation of a key within a predetermined second group of keys, and partial address signals uniquely identifying the activation of a key within a predetermined third group of keys; a read only memory providing as an output multibit codes in response to memory locations addressed by the partial address signals and a third signal (OHLFl), a given arrangement of partial address signals defining a word location in a first half of the memory when the OHLFl signal is true and a corresponding word location in a second half of the memory when the OHLFl signal is false; a latch responsive to the output codes from the read only memory and the OHLFl signal, the output codes from the read only memory being latched when the OHLFl signal changes from true to false and being output by the latch so long as the OHLFl signal remains false; at least two flip flops defining in combination at least four mutually exclusive states; means responsive to the ORSTK signal and the OKDl signal for sequencing the flip flops through at least first, second, third and last states respectively, the flip flops being (1) constrained to the first state in the absence of an OKDl signal, (2) sequenced from the first state to the second state only after a sufficient time delay to allow dissipation of keyboard switch bounce, (3) sequenced from the second state to the third state only after sufficient time delay to permit latching of an output code from the first half of the read only memory and establishment of an output from the second half of the read only memory, (4) sequenced from the third state to the last state only after sufficient time to allow the transfer of output codes from the key input system to a data receiving device, and (5) sequenced from the last state to the first state only at the conclusion of each first and subsequent period of time throughout all of which both the OKDl and ORPTK signals remain true, said first period of time being of sufficient duration to allow an operator time to release an activated key under normal keyboard operation circumstances; means responsive to the two flip flops for generating a true OHLFl signal only when the flip flops are in the first state; and means responsive to the flip flops for generating a true data strobe signal to cause transfer of output codes from the latch and the read only memory only when the flip flops are in the third state.