Shift unit for variable data widths

Claim 2

Apparatus for shifting a group of data bits of variable widths a selected number of positions X in one of two directions comprising a shift path having N lines, means for storing the group of data bits in an ordered sequence of sets of N bits each, first logical circuits responsive to a binary value equal to X for shifting each set of N bits in the group X positions in said one direction to form a first type of partial result, second logical circuits responsive to a binary value equal to the Ns complement of X for shifting in the other direction each set of N bits, except the last set in said sequence to be shifted, a number of positions equal to the Ns complement of X to form a second type of partial result, and OR circuits logically combining each second type of partial result with a corresponding first type of partial result derived from the next succeeding set in said sequence to be shifted.

Claim 3

The apparatus of claim 1 wherein the shift path comprises a group of logical circuit elements for each binary bit position of the value X, N input and N output lines for each group, each group of elements including a plurality of elements for each bit position of the path with inputs selectivley connected to the input lines for shifting input data a number of positions in either direction or not shifting; and gate inputs to each element in a group responsive to said first and second logical circuits for shifting input data in one direction or the other or neither direction.

Claim 4

Apparatus for shifting a group of data bits of variable widths a selected number of positions X in one of two directions comprising a shift path having N lines, means for storing the group of data bits in an ordered sequence of sets of N bits each, first logical circuits responsive to a binary value equal to X for shifting each set of N bits in the group X positions in said one direction to form a first type of partial result, second logical circuits responsive to a binary value equal to the binary complement of X for shifting in the other direction each set of N bits, except the last set in said sequence to be shifted, a number Of positions equal to the binary complement of X to form a second type of partial result, logical circuits for shifting each second type of partial results one position in said other direction to form corresponding third types of partial results, and OR circuits logically combining each third type of partial result with a corresponding first type of partial result derived from the next succeeding set in said sequence to be shifted.

Claim 5

Apparatus for shifting a group of data bits of variable widths a selected number of positions X in one of two directions comprising a shift path having N lines, means for storing the group of data bits in an ordered sequence of sets of N bits each, first logical circuits responsive to a binary value equal to X for shifting each set of N bits in the group X positions in said one direction to form a first type of partial result, second logical circuits responsive to a binary value equal to the binary complement of X for shifting in the other direction each set of N bits, except the last set in said sequence to be shifted, a number Of positions equal to the binary complement of X to form a second type of partial result, logical circuits for shifting each second type of partial results one position in said other direction to form corresponding third types of partial results, and OR circuits logically combining each third type of partial result with a corresponding first type of partial result derived from the next succeeding set in said sequence to be shifted.

Claim 6

The apparatus of claim 3 wherein the shift path comprises a group of logical circuit elements for each binary bit position of the value X, N input and N output lines for each group, each group of elements including a plurality of elements for each bit position of the path with inputs selectively connected to the input lines for shifting input data a number of positions in either direction or not shifting; and gate inputs to each element in a group responsive to said logical circuits for shifting input data in one direction or the other or neither direction.

Claim 9

The method of claim 5 further comprising the step of producing a final result by logically combining the logically combined valid data bits with each other and with said last set of N bits in the ordered sequence.

Claim 10

The method of claim 5 wherein the step of shifting a number of positions equal to the Ns complement of X comprises the steps of shifting, in said opposite direction, a number of positions equal to the binary complement of X, and shifting, in said opposite direction, one additional position.

Claim 11

Circuit arrangement for shifting data of variable widths by one or several bits in one shift cycle, using a controlled logical switching network having an input, said circuit arrangement comprising first means for receiving a control signal (C), second means for receiving a shift amount (SA) by which the data bits applied to the input are to be shifted, third means for switching the shift amount (SA) from the true value to the complement value and vice versa in response to said control signal (C), said switching network responsive to said true and complement values of the shift amount for shifting data applied to its input to produce partial results, and means logically combining the partial results thus produced.

Claim 12

Circuit arrangement for shifting data of variable widths by one or several bits in one shift cycle, using a controlled logical switching network having an input, said circuit arrangement comprising first means for receiving a control signal (C), second means for receiving a shift amount (SA) by which the data bits applied to the input are to be shifted, third means for switching the shift amount (SA) from the true value to the complement value and vice versa in response to said control signal (C), said switching network responsive to said true and complement values of the shift amount for shifting data applied to its input to produce partial results, and means logically combining the partial results thus produced.

Claim 13

Circuit arrangement in accordance with claim 8, wherein said third means consists of exclusive-OR circuits (1, 2, and 3), one input of which is controlled by one bit each of the shift amount (SA), the other input being commonly controlled, via a line (4), by the complement control signal (C), and the output of which acts on a connected three-unit combine circuit in one row each of the logical switching network.

Claim 14

Circuit arrangement in accordance with claim 8, wherein for generating the 8th complement of a shift amount (SA) a bit of the shift amount (SA) having a value of 20 is directly applied, via a line (10), to a first three-unit control circuit, wherein this bit is additionally applied to an input of an AND-circuit (11) in a second row and to an input of an OR-circuit (12) in a third row, and wherein a bit of the shift amount (SA) having a value of 21 is fed, via a line (13), to exclusive-OR circuit (14) and to a second input of OR-circuit (12), while a bit of the shift amount (SA) having a value of 22 is applied to exclusive-OR circuit (15) in the third row of the combine circuit.