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US3781776A Expired / Lapsed US ⏱️ 0.0 years remaining

Solid state high speed scanning compensator switch for sonar

Assignee: United States Department of the Navy
•
Filing: 1972-05-22
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Granted: 1973-12-25
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Expires: 1992-05-22
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Abstract

Abstract A solid state high speed scanning compensator switch having a clock frequency source controlling a multiplicity of semiconductor switches in a prescribed manner to scan the outputs of hydrophones of a sonar receiver system by selecting a group of 16 adjacent outputs and to switch same into beam-forming delay lines, then steering the received beam in a rapid manner and passing the summed analog signals through a bandpass filter and at the same time providing scan synchronizing three-phase signals for producing a spiral sweep to provide sonar range and direction of a target on a display in relation to the hydrophone receivers.

Inventors

  • 👤 E Roeschlein
  • 👤 D Weiss
  • 👤 G Kuhn
  • 👤 K Peterson
  • 👤 K Weiss
  • 👤 D Zeph

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 15:13
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/52; G01S7/56; G01S7/62; G01S7/6218; G01S15/00; G01S15/02; G01S15/50; G01S15/52; G01S3/00; G01S3/80; G01S3/802; G01S3/809

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 299 words
A solid state high speed scanning compensator switch for sonar receivers comprising: a plurality of hydrophone signal inputs; circuit means coupled to said inputs capable of filtering, buffering and limiting said hydrophone signals individually and conducting same to an equal number of outputs therefrom; a solid state switch array having a plurality of control inputs and a plurality of signal outputs, said solid state switch array being coupled to said circuit means outputs; a demultiplexer having a plurality of signal inputs coupled respectively to said switch array signal outputs, having a three input control and a plurality of signal outputs; a delay line having a plurality of input taps coupled respectively to said plurality of demultiplexer outputs and having a single signal output being the sum of all delayed signals; a passive bandpass filter having an input coupled to said delay line output and having an output adapted to be coupled to a display device with a display system power system; an oscillator coupled through digital register circuits having outputs coupled to said control inputs of said switch array, having three outputs coupled to said three input control of said demultiplexer, and having outputs coupled through read only memory circuits and digital-to-analog converter circuits to produce analog voltage synchro reference signals, modulated by ramp function voltages and adapted for driving the beam of the display device, and test signal outputs coupled through test selector switch means to said circuit means to test continuity of simulated signals to the passive bandpass filter output whereby the oscillator provides proper digital frequencies on said digital register outputs to produce rapid scan switching of said switch array and demultiplexer and analog voltages to drive the synchro of the display device to produce target range and direction information of targets producing said hydrophone signals.
Claim 2
Dependent Claim 299 words
A solid state high speed scanning compensator switch for sonar receivers comprising: a plurality of hydrophone signal inputs; circuit means coupled to said inputs capable of filtering, buffering and limiting said hydrophone signals individually and conducting same to an equal number of outputs therefrom; a solid state switch array having a plurality of control inputs and a plurality of signal outputs, said solid state switch array being coupled to said circuit means outputs; a demultiplexer having a plurality of signal inputs coupled respectively to said switch array signal outputs, having a three input control and a plurality of signal outputs; a delay line having a plurality of input taps coupled respectively to said plurality of demultiplexer outputs and having a single signal output being the sum of all delayed signals; a passive bandpass filter having an input coupled to said delay line output and having an output adapted to be coupled to a display device with a display system power system; an oscillator coupled through digital register circuits having outputs coupled to said control inputs of said switch array, having three outputs coupled to said three input control of said demultiplexer, and having outputs coupled through read only memory circuits and digital-to-analog converter circuits to produce analog voltage synchro reference signals, modulated by ramp function voltages and adapted for driving the beam of the display device, and test signal outputs coupled through test selector switch means to said circuit means to test continuity of simulated signals to the passive bandpass filter output whereby the oscillator provides proper digital frequencies on said digital register outputs to produce rapid scan switching of said switch array and demultiplexer and analog voltages to drive the synchro of the display device to produce target range and direction information of targets producing said hydrophone signals.
Claim 3
Dependent Claim 66 words
A solid state high speed scanning compensator switch as set forth in claim 1 wherein said circuit means includes a plurality of bandpass filters, each capable of passing hydrophone received echo signals of the bandwidth of the transmitted signals and possible doppler frequency, and includes a plurality of buffers and limiters for providing a high impedance load and for protecting the solid state circuitry from overvoltage.
Claim 4
Dependent Claim 50 words
A solid state high speed scanning compensAtor switch as set forth in claim 2 wherein said delay line plurality of input taps are at points dividing said delay line into sections to produce suitable microsecond delays for proper beamforming, the end of said delay line constituting said delay line output.
Claim 5
Dependent Claim 52 words
A solid state high speed scanning compensator switch as set forth in claim 3 wherein said oscillator is a phase-locked oscillator with the frequency and phase of the display system power supply and said digital register circuits are shift registers and digital counters to divide downward the frequency of said phase-locked oscillator.
Claim 6
Dependent Claim 113 words
A solid state high speed scanning compensator switch as set forth in claim 4 wherein said read only memory circuits include two, each of which have digital memory representative of the function of angles, but one hundred and twenty degrees apart, and said digital-to-analog converters utilize one for each read only memory output which produce on the outputs thereof analog voltages representative of the function of said angles 120* apart, said read only memory output including a resistor-capacitor module for summing and inverting said read only memory outputs to produce on its outputs three analog voltage signals at phase relation 120* apart providing signals adapted for driving a synchro of said display device.
Claim 7
Dependent Claim 34 words
A solid state high speed scanning compensator switch as set forth in claim 5 wherein said digital counters divide said oscillator frequency down to 60 Hz per second for said read only memory circuits.
Claim 8
Dependent Claim 60 words
A solid state high speed scanning compensator switch as set forth in claim 6 wherein said digital counters divide said oscillator frequency down to 2,880 Hz per second for said switch array, said 2,880 Hz frequency being applied to a 48 stage shift register, the output of which is through a switch driver to said control input of switch array.
Claim 9
Dependent Claim 55 words
A solid state high speed scanning compensator switch as set forth in claim 7 wherein said digital counters divide said oscillator frequency down to 5,760 Hz per second for coupling through said switch means to said circuit means at the inputs to said buffer and limiter circuit to apply jam test signals into said receiver.

References Cited (Backward Citations)

US3676839A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-12-24 1977-06-25 1977-12-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-12-24 1981-06-25 1981-12-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-12-24 1985-06-25 1985-12-25 $7700.00 Window Closed / Lapsed

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