US3781701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing circuit for a color television receiver
Assignee: Motorola Solutions Inc
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Filing: 1971-03-04
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Granted: 1973-12-25
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Expires: 1991-03-04
Abstract
Abstract A color television receiver uses an integrated circuit to provide the subcarrier reference signals and ACC control voltage for the receiver. The circuit includes a first differential amplifier, unbalanced at the burst signal frequency, operated as the color reference oscillator to provide first and second differently phased output signals which are applied to a pair of differential steering gates. A phase-shift hue control of the color reference signal is obtained by adding selected outputs of the pair of differential steering gates. In addition, a differential amplifier is operated as a diodeless detector for deriving an ACC voltage from the oscillator output when burst signals are applied to the input of the oscillator.
Inventors
- 👤 G Cecchin
- 👤 F Hilbert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:30
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/643; H04N9/70; H04N9/71
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
218 words
A frequency-selective circuit including in combination: differential amplifier circuit means including first and second transistors, each having base, collector, and emitter electrodes, the emitter electrodes being coupled together; a current source coupled between a point of reference potential and said emitter electrodes of said first and second transistors; first and second input impedance means connected to said base electrodes of said first and second transistors, respectively; input circuit means connected to said input impedance means for applying input signals including signals of a predetermined frequency through said first and second impedance means to said base electrodes of said first and second transistors, the impedance values of said input impedance means causing said differential amplifier circuit means to provide common mode rejection to input signals; series resonant tuned circuit means resonant at the predetermined frequency connected between said base electrode of one of said first and second transistors and the reference potential point and responsive to input signals of the predetermined frequency applied thereto for unbalancing the differential amplifier circuit means to thereby provide amplified output signals in said collector electrodes of said transistors in response to input signals at the predetermined frequency; and output circuit means connected to said collector electrodes including means for obtaining output signals from said collector electrode of at least one of said transistors.
Claim 2
Dependent Claim
218 words
A frequency-selective circuit including in combination: differential amplifier circuit means including first and second transistors, each having base, collector, and emitter electrodes, the emitter electrodes being coupled together; a current source coupled between a point of reference potential and said emitter electrodes of said first and second transistors; first and second input impedance means connected to said base electrodes of said first and second transistors, respectively; input circuit means connected to said input impedance means for applying input signals including signals of a predetermined frequency through said first and second impedance means to said base electrodes of said first and second transistors, the impedance values of said input impedance means causing said differential amplifier circuit means to provide common mode rejection to input signals; series resonant tuned circuit means resonant at the predetermined frequency connected between said base electrode of one of said first and second transistors and the reference potential point and responsive to input signals of the predetermined frequency applied thereto for unbalancing the differential amplifier circuit means to thereby provide amplified output signals in said collector electrodes of said transistors in response to input signals at the predetermined frequency; and output circuit means connected to said collector electrodes including means for obtaining output signals from said collector electrode of at least one of said transistors.
Claim 3
Dependent Claim
49 words
The combination according to claim 1 further including regenerative feedback means coupled between the collector of one of the transistors and the input circuit means, the phase of signals passed by the feedback means being selected to cause the differential amplifier circuit means to oscillate at said predetermined frequency.
Claim 4
Dependent Claim
188 words
The combination according to claim 2 further including second differential amplifier means including third and fourth transistors, each having base, collector, and emitter electrodes; load circuit means coupled with said collector electrode of at least one of said third and fourth transistors; and a second current source coupled between the point of reference potential and said emitter electrodes of said third and fourth transistors; said collector electrode of said first transistor being coupled with said base electrode of said third transistor and said collector electrode of said second transistor being coupled with said base electrode of said fourth transistor, said third and fourth transistors being driven into limiting by the signals present on said collector electrodes of said first and second transistors; and wherein said feedback means includes a fifth transistor having base, collector, and emitter electrodes, and current limiting impedance means coupling said emitter electrode of said fifth transistor with said second current source, with said base electrode of said fifth transistor being coupled with said collector electrode of said first transistor and said collector electrode of said fifth transistor being coupled with said input circuit means.
References Cited (Backward Citations)
US3444476A
Cited
US3471794A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |