US3781670A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ac performance test for large scale integrated circuit chips
Assignee: International Business Machines Corp
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Filing: 1972-12-29
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Granted: 1973-12-25
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Expires: 1992-12-29
Abstract
Abstract After the circuit elements are formed in a large scale integrated circuit chip, but before the chip is personalized by a final metallization step in which the circuit elements are electrically interconnected in desired final circuit configuration, all of the circuit elements are temporarily interconnected in a recirculating test loop by a preliminary metallization step. Operating power is then applied to the circuit elements, and the frequency of the resultant selfoscillation of the loop is observed as an indication of the AC performance of the chip. If the chip passes the AC performance test, the temporary recirculating loop connections are interrupted, and the circuit elements are personalized by the final metallization step.
Inventors
- 👤 M Mcmahon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2273; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/31858
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
110 words
In the process of fabricating an integrated circuit in which a plurality of integrated circuit elements are formed in a semiconductor chip, an improved method for testing the AC performance of the circuit elements on the chip comprisIng the steps of: a. temporarily interconnecting a group of the circuit elements in a test circuit; b. applying D.C. operating potentials to the circuit elements in the test circuit; c. measuring the time for an electrical current to propagate through the test circuit; and d. interrupting the connections between at least some of the circuit elements in the test circuit prior to interconnnecting the circuit elements in a desired final circuit configuration.
Claim 2
Dependent Claim
110 words
In the process of fabricating an integrated circuit in which a plurality of integrated circuit elements are formed in a semiconductor chip, an improved method for testing the AC performance of the circuit elements on the chip comprisIng the steps of: a. temporarily interconnecting a group of the circuit elements in a test circuit; b. applying D.C. operating potentials to the circuit elements in the test circuit; c. measuring the time for an electrical current to propagate through the test circuit; and d. interrupting the connections between at least some of the circuit elements in the test circuit prior to interconnnecting the circuit elements in a desired final circuit configuration.
Claim 3
Dependent Claim
58 words
The improved method as defined in claim 1 wherein each of the circuit elements is capable of switching in both directions, and wherein said temporary interconnecting step comprises interconnecting an odd number of circuit elements in a recirculating loop test circuit in which the output of each circuit element is connected to the input of another circuit element.
Claim 4
Dependent Claim
51 words
The improved method as defined in claim 2 wherein the application of the operating potentials to the recirculation loop causes self-oscillation of the loop, and wherein said measuring step comprises measuring the frequency of self-oscillation of the recirculation loop as an indication of the AC performance of the interconnected circuit elements.
Claim 5
Dependent Claim
38 words
The improved method as defined in claim 1 wherein said interrupting step comprises interrupting the connections between all of the circuit elements in the test circuit prior to interconnecting the circuit elements in a desired final circuit configuration.
Claim 6
Dependent Claim
33 words
The improved method as defined in claim 1 wherein said temporary interconnecting step comprises temporarily interconnecting substantially all of said plurality of circuit elements in the chip into one or more test circuits.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |