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US3781482A
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US
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Pulse-correcting system for a telephone signaling system
Assignee: AG Communication Systems Corp
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Filing: 1972-01-31
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Granted: 1973-12-25
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Expires: 1992-01-31
Abstract
Abstract Pulse correcting circuitry, including three timing means, which provide minimum ''''break'''' and ''''make'''' pulse intervals at a receiving terminal. A first timer delays and subtracts a first predetermined time duration from the input pulse and delays the appearance of the pulse at the output of the first timer by this first predetermined time duration. A second timer is operatively connected with the first timer and prevents activation of the first timer for a second predetermined time interval in order to prevent operation of the pulse correcting circuitry on spurious pulses. Following the second predetermined time interval, the state of the outputs of the second timer are set and they are held for a third predetermined time interval. When the first and second timers permit an output to occur from the first timer, a third timer is activated and this timer insures that the pulse output has a minimum length. Where the input pulse to the first timer is longer than the minimum length, the output pulse is equal to the input pulse.
Inventors
- 👤 O Wisotzky
- 👤 T Blackburn
- 👤 R Urbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:08
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/32; H04Q1/36; H03; H03K; H03K5/00; H03K5/01; H03K5/04
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
412 words
Apparatus for correcting received telephone signaling pulses, which have at least a first predetermined pulse interval, said first predetermined pulse interval being less than a desired minimum corrected interval, to provide output pulses having at least minimum corrected ''''break'''' and ''''make'''' intervals, which comprises: an input timing means having an input connected to receive the signaling pulses, an output, means for subtracting the first predetermined time interval from said received signaling pulses, thereby providing a minimum ''''make'''' interval, said subtracting means having an output; and, a first logic means having a plurality of inputs one of which is operatively connected to the input of said timing means and a second input being operatively connected to the output of said subtracting means, said first logic means conditioned by said input signaling pulses and said subtracting means to apply the remainder of said received signaling pulse to said output; a guard function timing means having a first input operatively connected to the output oF said subtracting means, a first delay means having its input connected to the first said input of said guard means, said first delay means providing a second predetermined time interval; a second logic means responsive to said first delay means and having one output operatively connected to an input of said first logic means of the input timing means, said first delay means maintaining the output state of said second logic means for said second predetermined time interval after the signaling pulse appears at the output of said subtracting means, thereby preventing splits having less than a pre-established duration from affecting the output of said second logic means; and, a second delay means providing a third predetermined time interval, said second delay means being operatively connected between said first delay means and said second logic means and being activated by said first delay means at the end of the second predetermined time interval to hold the output states of said second logic means for the third predetermined time interval; and an output timing means having an input operatively connected to the output of the first logic means of said input timing means, an output, a variable delay means, a third logic means having one input operatively connected to the output of said input timing means and another input operatively connected to said variable delay means, which means adds a variable time interval to the output pulse interval from the output timing means, thereby obtaining at least the minimum ''''break'''' interval.
Claim 2
Dependent Claim
412 words
Apparatus for correcting received telephone signaling pulses, which have at least a first predetermined pulse interval, said first predetermined pulse interval being less than a desired minimum corrected interval, to provide output pulses having at least minimum corrected ''''break'''' and ''''make'''' intervals, which comprises: an input timing means having an input connected to receive the signaling pulses, an output, means for subtracting the first predetermined time interval from said received signaling pulses, thereby providing a minimum ''''make'''' interval, said subtracting means having an output; and, a first logic means having a plurality of inputs one of which is operatively connected to the input of said timing means and a second input being operatively connected to the output of said subtracting means, said first logic means conditioned by said input signaling pulses and said subtracting means to apply the remainder of said received signaling pulse to said output; a guard function timing means having a first input operatively connected to the output oF said subtracting means, a first delay means having its input connected to the first said input of said guard means, said first delay means providing a second predetermined time interval; a second logic means responsive to said first delay means and having one output operatively connected to an input of said first logic means of the input timing means, said first delay means maintaining the output state of said second logic means for said second predetermined time interval after the signaling pulse appears at the output of said subtracting means, thereby preventing splits having less than a pre-established duration from affecting the output of said second logic means; and, a second delay means providing a third predetermined time interval, said second delay means being operatively connected between said first delay means and said second logic means and being activated by said first delay means at the end of the second predetermined time interval to hold the output states of said second logic means for the third predetermined time interval; and an output timing means having an input operatively connected to the output of the first logic means of said input timing means, an output, a variable delay means, a third logic means having one input operatively connected to the output of said input timing means and another input operatively connected to said variable delay means, which means adds a variable time interval to the output pulse interval from the output timing means, thereby obtaining at least the minimum ''''break'''' interval.
Claim 3
Dependent Claim
196 words
Apparatus in accordance with claim 1 in which the subtracting means of the input timing means further comprises: an input gating means having a plurality of inputs and an output, one input being connected to receive the input signaling pulse and another input being connected to the output of said input timing means, said gating means providing an output of one binary logic state when the inputs are both of one like state and of the opposite binary logic state for all other input conditions; a time delay network having an input connected to the output of the input gating means, and an output, said time delay network being activated by the appearance of a pulse at the input to the gating means so that a first predetermined time interval is subtracted from the signaling pulse when the inputs to said input gating means are in said one like state; and an output gating means having a plurality of inputs and an output, one said input being connected to the output of said second logic means in said guard function timing means and another said input being connected to the output of said time delay network.
Claim 4
Dependent Claim
17 words
Apparatus as claimed in claim 2 in which the input gating means comprises a two input NAND-gate.
Claim 5
Dependent Claim
151 words
Apparatus as claimed in claim 3 in which the time delay network further comprises: a first switching means having an input and an output, the switching means being responsive to the input signaling pulse such that the switching means changes state and holds the change in state only during the first predetermined time interval; a first timing capacitor having one lead connected to the output of the input gating means and the other lead connected to the input of said switching means, said capacitor being charged when the output of the input gating means is in said opposite binary logic state; and a first resistor having one end connected to the output of said switching means and the other end connected to ground, said first resistor providing a discharge path for said timing capacitor when said switching means is in said one like state thereby creating said first predetermined time interval.
Claim 6
Dependent Claim
73 words
Apparatus in accordance with claim 4 in which the time delay network further comprises: a second resistor having one end connected to the output of said input gating means and the other end connected to ground; said second resistor providing a second discharge path for said timing capacitor when the Input signaling pulse momentarily is interrupted, said second discharge path providing a slower discharge rate than said first discharge path to integrate splits.
Claim 7
Dependent Claim
18 words
Apparatus in accordance with claim 1 in which the first logic means further comprises a three input NAND-gate.
Claim 8
Dependent Claim
263 words
Apparatus in accordance with claim 1 in which the guard function timing means further comprises: a first inverting means having an input connected to the output of the subtracting means of said input timing means and an output; a first time delay network providing a second predetermined time interval, having an input connected to the output of said first inverting means and an output; a second inverting means having an input connected to the output of said first delay means to delay inversion of an input binary state at the output of the second inverting means by said second predetermined time interval; a second time delay network having an input connected to the output of said second inverting means and an output, said second delay network providing the third predetermined time interval; a third inverting means having an input connected to the output of said second time delay network and an output, said third inverting means providing a change in state after said second predetermined time interval and maintaining said change in state at its output for the duration of said third predetermined time interval; and a second logic means having two inputs and two outputs, one said input being connected to the output of said third inverting means and the other said input being connected to the output of said output timing means, one said output being operatively connected to one input of the first logic means and the second output being operatively connected to the subtracting means of said input means and to the variable delay means of said output means.
Claim 9
Dependent Claim
207 words
Apparatus in accordance with claim 7 in which said second time delay network further comprises: a fourth inverting means having an input connected to the output of said second inverting means and an output; a second switching means having an output connected to the input of said third inverting means and an input; a second timing capacitor connected between the output of said fourth inverting means and the input of said second switching means; a resistor connected at one end to the input of said switching means and the other end converted to ground, the combination of timing capacitor and resistor holding said second switching means in one said state for said third predetermined time interval when a signaling pulse is applied at the input to the input timing means; a diode having its anode connected to the input of said second switching means and its cathode connected to the output of said second inverting means, said diode being forward biased following said second predetermined time interval which in turn causes said second switching means to change to said one state, said one state being maintained by the timing capacitor-resistor combination so that the one state is held during the first, second and third predetermined time intervals.
Claim 10
Dependent Claim
156 words
Apparatus in accordance with claim 8 in which said second logic means of the guard function timer further comprises: a first NAND-gate having an output and two inputs, a first input being connected to the output of said third inverting means, a second said input being connected to the output of said output timing means, and an output which is connected to an input of said subtracting means to condition the output of said subtracting means for said first predetermined time interval; a second NAND-gate having an output and two inputs, the first said input being connected to the output of said third inverting means and the second said input being connected to the output of said first NAND-gate of the second logic means, the output of said second NAND-gate is connected to one input of said first logic means in said input timing means and inhIbits the logic means during said second predetermined time interval.
Claim 11
Dependent Claim
224 words
Apparatus as claimed in claim 1 in which the third delay means further comprises: a first logic circuit having an output and two inputs, the first input being connected to the output of said input timing means and the other input being connected to the output of said output timing means, the output changing state only when both inputs are of one like state but not for other input conditions; a voltage divider having one end connected to ground, the other end connected to the output of the input timing means, and the voltage divider junction connected to the output of said first logic circuit; a third switching means having an input and an output; a third timing capacitor having one lead connected to the output of said first logic circuit and the other input connected to the input of said third switching means, said third timing capacitor being charged such that the voltage at the output of the first logic circuit is positive with respect to the input of the third switching means, the change in potential caused by the input to said output timing means going from a first binary logic state to the other logic state changes the state of the third switching means and the change on the third timing capacitor holds this condition for a fourth predetermined time interval.
Claim 12
Dependent Claim
57 words
Apparatus as claimed in claim 10 in which the input signaling pulse exceeds a minimum ''''break'''' interval and said first logic circuit is caused to change state, the output of which adds charge to said third timing capacitor to increase the fourth predetermined time interval to a value that is equal to said first predetermined time interval.
Claim 13
Dependent Claim
103 words
Apparatus as claimed in claim 10 in which the duration of the input signaling pulse equals or exceeds that of said third predetermined time interval, so that said guard function timing means times out, the second output of the output logic means of the guard function timer changes state, said second output being connected to the junction of said third timing capacitor and said third switching means; the change in state of said output logic reduces the charging rate of said third timing capacitor which increases the fourth predetermined time duration to a value that is greater than said first predetermined time interval.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |