Analog-to-digital wattmeter multiplier

Claim 2

In a quarter sQuare multiplier for receiving two analog input signals representative of a multiplier and a multiplicand and producing a digital output product signal including: means for adding said two analog input signals to produce a sum signal, means for subtracting one of said two analog input signals from the other for producing a difference signal, a pair of pulse forming channels, and digital difference means for obtaining the difference between the number of pulses in said pulse forming channels in a given time interval, the improvement wherein each of pulse forming channels comprises: switching means for combining said sum signal or said difference signal with reference signals of opposite polarity to produce a pair of combined signals, an integrating amplifier having an input for receiving said pair of combined signals, said amplifier integrating one of said pair of combined signals to produce an integrated output signal which ramps in one direction toward a first predetermined level and then integrating the other of said pair of combined signals to produce an integrated output signal which ramps in the other direction toward a second predetermined level, and detector means responsive to said integrated output signal for actuating said switching means to produce a pulse for each cycle of integration, the frequency of the pulses being related to the square of said sum signal and the square of said difference signal.

Claim 3

The apparatus recited in claim 1 wherein said first channel comprises: means for combining said sum signal Vs with a reference voltage VDC to produce a first alternating signal having a frequency fs FO ( 1 - (vs/VDC)2 ) where FO is the zero input operating frequency, and wherein said second channel comprises: means for combining said difference signal Vs with said reference voltage to produce a second alternating signal having a frequency fd FO ( 1 - (Vd/VDC)2 )

Claim 4

The apparatus recited in claim 1 wherein said digital difference means is a reversible counter, said first train of pulses being applied to said counter to count in a first direction and said second train of pulses being applied to said counter to count in the opposite direction.

Claim 5

An A.C. digital wattmeter using a quarter square multiplier for multiplying a multiplicand signal representative of an alternating voltage by a multiplier signal representative of alternating current, comprising: means for adding said multiplicand signal and said multiplier signal for producing a sum signal, means for subtracting one from the other of said multiplicand and said multiplier signals for producing a difference signal, means for squaring said sum signal and said difference signal, including, means for generating a reference signal having equal positive and negative potential, first switching means for combining said sum signal with said reference signal, a first integrating amplifier squarer for alternately integrating in one direction said sum signal and said reference signal of positive potential to a predetermined level and subsequently integrating in the opposite direction and said sum signal and said reference signal of negative potential to another predetermined level thus completing a cycle of integration, each cycle of integration producing a pulse of binary significance in a first series of pulse counts per unit of time having a frequency representative of said sum signal squared, first detector means responsive to the integrating output signal for actuating said first switching means, second switching means for combining said difference signal with said reference signal, a second integrating amplifier squarer for integrating in one direction said difference signal and said reference signal of positive potential to said predetermined level and integRating in the opposite direction said difference signal and said reference signal of negative potential to said another predetermined level thus completing a cycle of integration, each cycle of integration producing a pulse of binary significance in a second series of pulse counts per unit of time having a frequency representative of said difference signal squared, second detector means responsive to the output of said second integrating amplifier for actuating said second switching means, and means including a reversible counter for subtracting pulse counts in said second series of pulses from pulse counts in said first series of pulses for deriving a digital product signal per unit of time from multiplicand and multiplier signal.

Claim 6

An A.C. digital wattmeter using a quarter square multiplier for multiplying a multiplicand signal representative of an alternating voltage by a multiplier signal representative of alternating current, comprising: means for adding said multiplicand signal and said multiplier signal for producing a sum signal, means for subtracting one from the other of said multiplicand and said multiplier signals for producing a difference signal, means for squaring said sum signal and said difference signal, including, means for generating a reference signal having equal positive and negative potential, first switching means for combining said sum signal with said reference signal, a first integrating amplifier squarer for alternately integrating in one direction said sum signal and said reference signal of positive potential to a predetermined level and subsequently integrating in the opposite direction and said sum signal and said reference signal of negative potential to another predetermined level thus completing a cycle of integration, each cycle of integration producing a pulse of binary significance in a first series of pulse counts per unit of time having a frequency representative of said sum signal squared, first detector means responsive to the integrating output signal for actuating said first switching means, second switching means for combining said difference signal with said reference signal, a second integrating amplifier squarer for integrating in one direction said difference signal and said reference signal of positive potential to said predetermined level and integRating in the opposite direction said difference signal and said reference signal of negative potential to said another predetermined level thus completing a cycle of integration, each cycle of integration producing a pulse of binary significance in a second series of pulse counts per unit of time having a frequency representative of said difference signal squared, second detector means responsive to the output of said second integrating amplifier for actuating said second switching means, and means including a reversible counter for subtracting pulse counts in said second series of pulses from pulse counts in said first series of pulses for deriving a digital product signal per unit of time from multiplicand and multiplier signal.