US3778640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal voltage level translating circuit
Assignee: International Business Machines Corp
•
Filing: 1972-07-03
•
Granted: 1973-12-11
•
Expires: 1992-07-03
Abstract
Abstract A signal voltage level translating circuit receives an input electrical signal having predetermined voltage swings about a first predetermined voltage level and translates the voltage level of the signal so that at the output there is provided an output electrical signal having the same voltage swings about a second predetermined voltage level translated with respect to the first voltage level. An input transistor has its base connected to the input node and its emitter connected to one end of a first impedance element having its other end connected to the collector of a current source transistor. A fixed reference voltage is applied to the base of a reference voltage transistor having its emitter connected to one end of a second impedance element having an impedance equal to that of the first impedance element. The other end of the second impedance element is connected to the collector of a diode-connected transistor having its base connected to the base of the current source transistor. The emitter of the diode-connected transistor is connected to the emitter of the current source transistor. If implemented in the form of a monolithic integrated circuit, the diode-connected transistor and current source transistor may have the same base and the same emitter. The translated signal is taken at the output where the first impedance element is connected to the collector of the current source transistor.
Inventors
- 👤 D Tewarson
- 👤 S Platt
- 👤 J Pomeranz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/003; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
193 words
A signal voltage level translating circuit comprising Input means for receiving an electrical signal having predetermined voltage swings about a first predetermined voltage level, impedance means having a predetermined impedance and having one end connected to said input means, a substantially constant current source connected to the other end of said impedance means for supplying a relatively constant current therethrough, an output node connected to said other end of said impedance means for transmitting said signal with said predetermined voltage swings about a second predetermined voltage level translated with respect to said first predetermined level, said impedance means comprising a resistor having a predetermined resistance, said current source comprising a transistor having a collector connected to said output node and to said other end of said impedance means, said input means comprising an input node for receiving said electrical signal, an input transitor having a base connected to said input node and having an emitter connected to said one end of said impedance means, and reference voltage means independent of said input means, and for controlling the magnitude of said constant current in response to a reference voltage independent of said electrical signal.
Claim 2
Dependent Claim
193 words
A signal voltage level translating circuit comprising Input means for receiving an electrical signal having predetermined voltage swings about a first predetermined voltage level, impedance means having a predetermined impedance and having one end connected to said input means, a substantially constant current source connected to the other end of said impedance means for supplying a relatively constant current therethrough, an output node connected to said other end of said impedance means for transmitting said signal with said predetermined voltage swings about a second predetermined voltage level translated with respect to said first predetermined level, said impedance means comprising a resistor having a predetermined resistance, said current source comprising a transistor having a collector connected to said output node and to said other end of said impedance means, said input means comprising an input node for receiving said electrical signal, an input transitor having a base connected to said input node and having an emitter connected to said one end of said impedance means, and reference voltage means independent of said input means, and for controlling the magnitude of said constant current in response to a reference voltage independent of said electrical signal.
Claim 3
Dependent Claim
61 words
A signal voltage level translating circuits as recited in claim 1 wherein said reference means comprises a reference voltage node for receiving a reference voltage at said first predetermined voltage level, a reference voltage transistor having a base connected to said reference voltage node and having an emitter, and circuit means connecting said reference voltage transitor emitter to said current source.
Claim 4
Dependent Claim
56 words
A signal voltage translating circuit as recited in claim 2 wherein said circuit means comprises a pair of impedances connected in series at a common node, and means connecting said common node to said current source for determining the magnitude of the current of said current source in response to the voltage of said common node.
Claim 5
Dependent Claim
32 words
A signal voltage level translating circuit as recited in claim 3 wherein on of said pair of impedances is a resistance and the other of said pair of impedances as a diode.
Claim 6
Dependent Claim
27 words
A signal level translating circuit as recited in claim 4 wherein said resistance has an impedance substantially equal to said predetermined impedance of said first-recited impedance means.
Claim 7
Dependent Claim
70 words
A circuit as receited in claim 5 wherein said current source transistor has an emitter, a voltage source connected to said last-recited emitter, a driver transistor having a collector, a base, and an emitter, a first conductor connectedd between said output node and said driver transistor base, a second conductor connected between said voltage source and said driver transistor emitter, and a driver output connected to said driver transistor collector.
Claim 8
Dependent Claim
69 words
A circuit as recited in claim 1 wherein said current source transistor has an emitter, a voltage source connected to said last-recited emitter, a driver transitor having a collector, base, and an emitter, a first conductor connected between said output node and said drive transistor base, a second conductor connected between said voltage source and said driver transistor emitter, and a driver output connected to said driver transistor collector.
Claim 9
Dependent Claim
60 words
A circuit as recited in claim 9 and comprising a fifth transistor having a collector, a base, and an emitter, a first conductor connected between said output node and said fifth transistor base, a second conductor connected between said emitters of said fourth and second transistors and said fifth transistor emitter, and an output connected to said fifth transistor collector.
Claim 10
Dependent Claim
251 words
A signal voltage level translating circuit comprising an input node for receiving an electrical signal having predetermined voltage swings about a first predetermined voltage level, a first transistor having a base and an emitter, a first impedance element having one end connected to said emitter, a second transistor having a base and an emitter and having a collector connected to the other end of said first impedance element, a reference voltage node independent of said input node for receiving independently of said input signal a reference voltage at said first predetermined voltage level, a third transistor haivng a base and an emitter, a second impedance element having one end connected to said third transistor emitter and having an impedance substantially equal to the impedance of said first impedance element, a fourth transistor having a collector connected to the other end of said second impedance element and having a base and an emitter, first means shorting said base and collector of said fourth transistor, second means connecting said fourth transistor base to said second transistor base, third means connecting said fourth transistor emitter to said second transistor emitter, an output node for transmitting said signal with said predetermined voltage swings about a second predetermined voltage level translated with respect to said first predetermined voltage level, fourth means connecting said output node to said second transistor collector, fifth means connecting said first transistor base to one of said nodes, and sixth means connecting said third transistor base to the other of said nodes.
Claim 11
Dependent Claim
251 words
A signal voltage level translating circuit comprising an input node for receiving an electrical signal having predetermined voltage swings about a first predetermined voltage level, a first transistor having a base and an emitter, a first impedance element having one end connected to said emitter, a second transistor having a base and an emitter and having a collector connected to the other end of said first impedance element, a reference voltage node independent of said input node for receiving independently of said input signal a reference voltage at said first predetermined voltage level, a third transistor haivng a base and an emitter, a second impedance element having one end connected to said third transistor emitter and having an impedance substantially equal to the impedance of said first impedance element, a fourth transistor having a collector connected to the other end of said second impedance element and having a base and an emitter, first means shorting said base and collector of said fourth transistor, second means connecting said fourth transistor base to said second transistor base, third means connecting said fourth transistor emitter to said second transistor emitter, an output node for transmitting said signal with said predetermined voltage swings about a second predetermined voltage level translated with respect to said first predetermined voltage level, fourth means connecting said output node to said second transistor collector, fifth means connecting said first transistor base to one of said nodes, and sixth means connecting said third transistor base to the other of said nodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |