US3778638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency-to-voltage converter having high noise immunity
Assignee: General Electric Co
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Filing: 1972-11-09
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Granted: 1973-12-11
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Expires: 1992-11-09
Abstract
Abstract An electronic frequency-to-voltage converter employs a retriggerable second timing circuit for detecting a monitored predetermined frequency input slightly below a specific rated frequency. The second timing circuit is interconnected with a main timing circuit through digital logic circuitry and overrides the main timer when the input exceeds the predetermined frequency and also causes the converter output voltage to abruptly rise to, and remain at, a voltage amplitude corresponding to the rated frequency input. Noise interference is eliminated by interconnecting a binary counter in the circuit for counting up to a predetermined number of input pulses which may include noise, during the timing cycle of the second timing circuit. The overriding function of the second timing circuit is thereby delayed until the predetermined number of pulses have occurred during the timing cycle of the second timing circuit.
Inventors
- 👤 P Garratt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:29
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/02; H03D3/04; G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/4802; G01R; G01R23/00; G01R23/02; G01R23/06; H03K; H03K9/00; H03K9/06
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
235 words
An improved frequency-to-voltage converter comprising a first flip-flop having a set input connected to an input terminal of the converter to which is applied a pulsed voltage waveform having a frequency proportional to the value of a parameter being monitored, a first timing circuit having an input connected to a first output of said first flip-flop, and having an output connected to a reset input of said first flip-flop, a complementary second output of said first flip-flop connected to an output circuit including filter means for smoothing the flip-flop output to an average DC voltage level proportional to the frequency of the input pulsed voltage waveform, the improvement comprising a retriggerable second timing circuit for detecting the parameter value at a predetermined magnitude slightly lower than a rated value thereof, said second timing circuit having an input connected to the input terminal of the converter whereby said second timing circuit is retriggered and remains in its timing state during the time interval in which the value of the monitored parameters exceeds the predetermined value, and first digital logic circuit means interconnected with the second output of said first flip-flop, and with the input terminal of the converter, and with a first output of said second timing circuit and said output circuit for overriding the output of said first flip-flop during the time interval in which the value of the monitored parameter exceeds the predetermined value.
Claim 2
Dependent Claim
235 words
An improved frequency-to-voltage converter comprising a first flip-flop having a set input connected to an input terminal of the converter to which is applied a pulsed voltage waveform having a frequency proportional to the value of a parameter being monitored, a first timing circuit having an input connected to a first output of said first flip-flop, and having an output connected to a reset input of said first flip-flop, a complementary second output of said first flip-flop connected to an output circuit including filter means for smoothing the flip-flop output to an average DC voltage level proportional to the frequency of the input pulsed voltage waveform, the improvement comprising a retriggerable second timing circuit for detecting the parameter value at a predetermined magnitude slightly lower than a rated value thereof, said second timing circuit having an input connected to the input terminal of the converter whereby said second timing circuit is retriggered and remains in its timing state during the time interval in which the value of the monitored parameters exceeds the predetermined value, and first digital logic circuit means interconnected with the second output of said first flip-flop, and with the input terminal of the converter, and with a first output of said second timing circuit and said output circuit for overriding the output of said first flip-flop during the time interval in which the value of the monitored parameter exceeds the predetermined value.
Claim 3
Dependent Claim
71 words
The improved frequency-to-voltage converter set forth in claim 1 wherein said first digital logic circuit means having a first input connected to the second output of said first flip-flop, a second input connected to the input terminal of the converter, and a third input connected to the first output of said second timing circuit, said first digital logic circuit means having an output connected to an input of said output circuit.
Claim 4
Dependent Claim
41 words
The improved frequency-to-voltage converter set forth in claim 2 wherein the output of said first digital logic circuit means is directly connected to the input of said output circuit and the second output of said first flip-flop is indirectly connected thereto.
Claim 5
Dependent Claim
29 words
The imrpoved frequency-to-voltage converter set forth in claim 1 wherein the timing duration of said second timing circuit is greater than the timing duration of said first timing circuit.
Claim 6
Dependent Claim
120 words
The improved frequency-to-voltage converter set forth in claim 2 wherein said first digital logic circuit means comprises a first NAND logic gate having a first input connected to the input terminal of the converter thereby forming the second input of said first digital logic circuit means, said first NAND gate having a second input connected to the first output of said second timing circuit thereby forming the third input of said first digital logic circuit means, said first NAND gate providing a pulsed output in response to the pulsed voltage waveform applied to the input terminal of the converter only during the timing interval of said second timing circuit when the value of the monitored parameter exceeds the predetermined value.
Claim 7
Dependent Claim
126 words
The improved frequency-to-voltage converter set forth in claim 5 wherein said first digital logic circuit means further comprises a second flip-flop having a set inpUt connected to an output of said first NAND gate and having a reset input connected to the first output of said second timing circuit thereby further forming the third input of said first digital logic circuit means, said second flip-flop switching its output to the set state thereof in response to the first pulsed output of said first NAND gate during the timing interval of said second timing circuit when the value of the monitored parameter exceeds the predetermined value and switching its output to the reset state at the end of the corresponding timing interval of said second timing circuit.
Claim 8
Dependent Claim
171 words
The improved frequency-to-voltage converter set forth in claim 6 wherein said first digital logic circuit means further comprises a NOR logic gate having a first input connected to the second output of said first flip-flop thereby forming the first input of said first digital logic circuit means, a second input of said NOR gate connected to an output of said second flip-flop, an output of said NOR gate connected to an input of said output circuit thereby forming the output of said first digital logic circuit means, output of said NOR gate corresponding to an alternately set and reset output of said first flip-flop during the time interval in which the value of the monitored parameter is less than the predetermined value, the output of said NOR gate being switched to and remaining in its high state thereby overriding the output of said first flip-flop during the time interval in which the value of the monitored parameter exceeds the predetermined value and said second timing circuit remains in its timing state.
Claim 9
Dependent Claim
110 words
The improved frequency-to-voltage converter set forth in claim 5 and further comprising a capacitor having an input connected to the input termianl of the converter and having an output connected to each of the set input of said first flip-flop, the input of said second timing circuit and the first input of said first NAND gate for converting the input pulsed voltage waveform to corresponding voltage spikes for triggering the timing of said second timing circuit and for providing like voltage spikes at the output of said first NAND gate during the timing interval of said second timing circuit when the value of the monitored parameter exceeds the predetermined value.
Claim 10
Dependent Claim
52 words
The improved frequency-to-voltage converter set forth in claim 8 and further comprising an inverter having an input connected to the output of said capacitor and an output connected to each of said second timing circuit and the first input of said first NAND gage for inverting the polarity of the voltage spikes.
Claim 11
Dependent Claim
20 words
The improved frequency-to-voltage converter set forth in claim 1 wherein said first timing circuit is a unijunction transistor timing circuit.
Claim 12
Dependent Claim
19 words
The improved frequency-to-voltage converter set forth in claim 1 wherein said second timing circuit is a retriggerable monostable multivibrator.
Claim 13
Dependent Claim
56 words
The improved frequency-to-voltage converter set forth in claim 7 wherein said output circuit further includes a precision analog switch having a first input connected to the output of said NOR gate and a second input connected to a stable reference voltage source, output of said precision analog switch connected to an input of said filter means.
Claim 14
Dependent Claim
22 words
The improved frequency-to-voltage converter set forth in claim 1 wherein the filter means in said output circuit is a low pass filter.
Claim 15
Dependent Claim
101 words
The imrpoved frequency-to-voltage converter set forth in claim 1 and further comprising second digital logic circuit means interconnected with an output of said second timing circuit and with said first digital logic circuit means for delaying the overriding function established by said first digital logic circuit means and said second timing circuit until a predetermined number of voltage pulses have been applied to the input terminal of the converter and which may include a combination of the pulsed voltage waveform having frequency proportional to the monitored parameter as well as undesured noise undesired thereby obtain a high noise immunity frequency-to-voltage converter.
Claim 16
Dependent Claim
82 words
The improved frequency-to-voltage converter having high noise immunity set forth in claim 14 wherein said second digital logic circuit means comprises a multi-stage binary counter having a reset input connected to an output of said second timing circuit whereby said binary counter is reset whenever said second timing circuit completes a timing cycle, and a second NAND logic gate having inputs connected to outputs of said binary counter and having an output connected to inputs of said first digital logic circuit means.
Claim 17
Dependent Claim
150 words
The improved frequency-to-voltage converter having high noise immunity set forth in claim 15 wherein said first digital logic circuit means comprises a first NAND logic gate having a first input connected to the first output of said second timing circuit and a second input connected to the input terminal of the converter and a third input connected to the output of said second NAND gate, output of said first NAND gate connected to a count input of said multi-stage binary counter, and a NOR logic gate having a first input connected to the complementary second output of said first flip-flop and having a second input connected to the output of said second NAND gate and having an output connected to an input of said output circuit whereby the overriding function is delayed until a maximum count has been established in said binary counter to thereby provide the high noise immunity.
Claim 18
Dependent Claim
57 words
The improved frequency-to-voltage converter having high noise immunity set forth in claim 16 and further comprising an inverter having an input connected to an output of said first NAND gate and an output connected to the count input of said binary counter for reversing the polarity of voltage pulses at the output of said first NAND gate.
Claim 19
Dependent Claim
176 words
The improved frequency-to-voltage converter having high noise immunity set forth in claim 14 wherein said first digital logic circuit means comprises a first AND logic gate having a first input connected to the the first output of said second timing circuit and having a second input connected to the input terminal of the converter, and an OR logic gate having a first input connected to the first output of said first flip-flop and having an output connected to an input of said output circuit, said second digital logic circuit means comprises a binary counter having a count input connected to an output of said first AND gate and having a reset input connected to a complementary second output of said second timing circuit, a second AND gate having inputs connected to outputs of said binary counter and an output connected to a second input of said OR gate, and an inverter having an input connected to the output of said second AND gate and an output connected to a third input of said first AND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |