US3777277A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Discrete step frequency sweep
Assignee: United States Department of the Navy
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Filing: 1973-02-23
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Granted: 1973-12-04
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Expires: 1993-02-23
Abstract
Abstract A frequency sweep generator for generating a repetitive series of constant amplitude, stable, discrete step frequency outputs. Eight crystal oscillators of increasingly higher frequencies are divided into odd and even groups of four oscillators each. Dual selecting circuits each comprising a three bit binary counter triggered by a periodic step command, a two bit decoder and four sampling gates, alternately select in numerical sequence one oscillator output from each of the groups. A delay circuit delays the step command one full period before triggering the even group binary counter. Each oscillator output is energized for a duration of two step command periods and the least significant bit of the odd group binary counter alternately selects the odd and even groups of parallel gates for a single step command period thus allowing each frequency output to warm up and stabilize due to advanced turn-on of the next required oscillator prior to sampling its output. The outputs of eight sampling gates are connected in common to provide a serial output.
Inventors
- 👤 R Naber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:55
CPC Classifications
H; H03; H03B; H03B23/00; H03B2200/00; H03B2200/006; H03B2200/0092
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A frequency sweep generator for producing a periodic series of discrete constant amplitude frequencies, comprising: first frequency selecting means connected to receive a periodic series of input pulses for sequentially selecting respective ones of a first plurality of discrete frequencies according to the number of said received input pulses, and providing outputs representative of said first plurality of discrete frequencies; delay means connected to receive said input pulses and for providing output pulses delayed one period; second frequency selecting means connected to receive said delayed pulses for sequentially selecting respective ones of a second plurality of discrete frequencies according to the number of said received delayed pulses and providing outputs representative of said second plurality of discrete frequencies; and sampling means connected to said first and second frequency selecting means for alternating sampling said outputs representative of said first and second pluralities of discrete frequencies according to the reception of said input pulses by said first frequency selecting means and for providing a common output.
Claim 2
Dependent Claim
165 words
A frequency sweep generator for producing a periodic series of discrete constant amplitude frequencies, comprising: first frequency selecting means connected to receive a periodic series of input pulses for sequentially selecting respective ones of a first plurality of discrete frequencies according to the number of said received input pulses, and providing outputs representative of said first plurality of discrete frequencies; delay means connected to receive said input pulses and for providing output pulses delayed one period; second frequency selecting means connected to receive said delayed pulses for sequentially selecting respective ones of a second plurality of discrete frequencies according to the number of said received delayed pulses and providing outputs representative of said second plurality of discrete frequencies; and sampling means connected to said first and second frequency selecting means for alternating sampling said outputs representative of said first and second pluralities of discrete frequencies according to the reception of said input pulses by said first frequency selecting means and for providing a common output.
Claim 3
Dependent Claim
95 words
A frequency sweep generator as defined in claim 1 wherein said first frequency selecting means comprises: a first binary counter for receiving said input pulses and for providing a first parallel binary code indicative of the number of input pulses; a first decoder for receiving all binary bits but the least significant bit of the first code and for selectively energizing one of a plurality of parallel outputs; and a first plurality of discrete freqeuncy oscillators for receiving said first decoder outputs and for providing said outputs representative of said first plurality of discrete frequencies.
Claim 4
Dependent Claim
20 words
A frequency sweep generator as defined in claim 2 wherein said first plurality of discrete frequency oscillators are crystal oscillators.
Claim 5
Dependent Claim
97 words
A frequency sweep generator as defined in claim 2 wherein said second frequency selecting means comprises: a second binary counter for receiving said delayed pulses and for providing a second parallel binary code indicative of the number of said delayed input pulses; a second decoder for receiving all binary bits but the least significant bit of the second code and for selectively energizing one of a plurality of parallel outputs; and a second plurality of discrete frequency oscillators for receiving said second decoder outputs and for providing said outputs representative of said second plurality of discrete frequencies.
Claim 6
Dependent Claim
21 words
A frequency sweep generator as defined in claim 4 wherein said first binary counter and said second binary counter are identical.
Claim 7
Dependent Claim
19 words
A frequency sweep generator as defined in claim 5 wherein said first decoder and said second decoder are identical.
Claim 8
Dependent Claim
20 words
A frequency sweep generator as defined in claim 6 wherein said second plurality of discrete frequency oscillators are crystal oscillators.
Claim 9
Dependent Claim
152 words
A frequency sweep generator as defined in claim 6 wherein said sampling means comprises: a first plurality of gates having a first input connected to receive said outputs representative of said first plurality of discrete frequencies and a second input connected to receive the least significant bit of said first binary code for enabling said first plurality of discrete frequencies to pass to outputs thereof; an inverter connected to receive the least significant bit of said first binary code and for inverting said bit to its alternate binary state; a second plurality of gates having a first input connected to receive said outputs representative of said second plurality of discrete frequencies and a second input connected to receive said inverted bit for enabling said second plurality of discrete frequencies to pass to the outputs thereof; and an output terminal commonly connected to said output of said first and second plurality of gates.
Claim 10
Dependent Claim
289 words
A frequency sweep generator for producing a periodic series of discrete constant amplitude frequencies, comprising: a first binary counter for receiving clock pulses and for providing a first parallel binary code indicative of the number of clock pulses; a first decoder for receiving all binary bits but the least significant bit of the first code and for selectively energizing one of a plruality of parallel outputs; a first plurality of discrete frequency oscillators for receiving respective ones of said first decoder outputs and for providing discrete frequency signal outputs in response thereto; a first plurality of gates for receiving the first plurality of oscillator outputs and said least significant bit and for passing respective ones of said discrete frequency signal outputs in response thereto; delay means for receiving said clock pulses and for providing output pulses delayed one period; a second binary counter for receiving said delayed pulses and for providing a second parallel binary code indicative of the number of said delayed clock pulses; a second decoder for receiving all binary bits but the least significant bit of the second code and for sElectively energizing one of a plurality of parallel outputs; a second plurality of discrete frequency oscillators for receiving respective ones of said second decoder outputs and for providing discrete frequency signal outputs in response thereto; an inverter for receiving said least significant bit of the first code and for inverting said bit to its alternate binary state; and a second plurality of gates for receiving the second plurality of oscillator outputs and said inverted bits and for passing respective ones of said discrete frequency signal outputs in response thereto, the outputs of said first and second pluralities of gates being connected to a common output.
Claim 11
Dependent Claim
289 words
A frequency sweep generator for producing a periodic series of discrete constant amplitude frequencies, comprising: a first binary counter for receiving clock pulses and for providing a first parallel binary code indicative of the number of clock pulses; a first decoder for receiving all binary bits but the least significant bit of the first code and for selectively energizing one of a plruality of parallel outputs; a first plurality of discrete frequency oscillators for receiving respective ones of said first decoder outputs and for providing discrete frequency signal outputs in response thereto; a first plurality of gates for receiving the first plurality of oscillator outputs and said least significant bit and for passing respective ones of said discrete frequency signal outputs in response thereto; delay means for receiving said clock pulses and for providing output pulses delayed one period; a second binary counter for receiving said delayed pulses and for providing a second parallel binary code indicative of the number of said delayed clock pulses; a second decoder for receiving all binary bits but the least significant bit of the second code and for sElectively energizing one of a plurality of parallel outputs; a second plurality of discrete frequency oscillators for receiving respective ones of said second decoder outputs and for providing discrete frequency signal outputs in response thereto; an inverter for receiving said least significant bit of the first code and for inverting said bit to its alternate binary state; and a second plurality of gates for receiving the second plurality of oscillator outputs and said inverted bits and for passing respective ones of said discrete frequency signal outputs in response thereto, the outputs of said first and second pluralities of gates being connected to a common output.
References Cited (Backward Citations)
US3226648A
Cited
US3573663A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-03 | 1977-06-04 | 1977-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-03 | 1981-06-04 | 1981-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-03 | 1985-06-04 | 1985-12-04 | $7700.00 | Window Closed / Lapsed |