US3777126A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Measurement transducer calculator interface
Assignee: Dietzgen Electronics Inc
•
Filing: 1972-05-03
•
Granted: 1973-12-04
•
Expires: 1992-05-03
Abstract
Abstract A measurement transducer/calculator interface for processing output signals from one or more measurement transducers for input to an electronic calculator. The interface is coupled for receiving and shaping pulse signals at the frequency generated by a measurement transducer. The data signals are processed, then temporarily accumulated in a buffer memory effectively compressing the data signals which are thereafter sequenced through a decoder into the calculator input at the highest rate for reliable keyboard entry into the calculator.
Inventors
- 👤 D Hoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:29
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/02; G06F15/025; G06F15/0275
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
127 words
A measurement transducer/calculator interface for processing output signals from one or more measurement transducers for input to an electronic calculator comprising: means for receiving and shaping data signals at the rate generated by a measurement transducer; means for scaling said signals; two phase readout clock means; means for synchronizing the processed data signals with the first phase of said readout clock to provide synchronized readout signals; buffer memory means for temporarily accumulating said synchronized readout signals; decoder means for decoding signals received from the buffer memory; and means for sequencing data signals from the buffer memory in synchronization with the second phase of the readout clock means and through the decoder into a calculator input at a rate commensurate with the input entry rate of the calculator.
Claim 2
Dependent Claim
127 words
A measurement transducer/calculator interface for processing output signals from one or more measurement transducers for input to an electronic calculator comprising: means for receiving and shaping data signals at the rate generated by a measurement transducer; means for scaling said signals; two phase readout clock means; means for synchronizing the processed data signals with the first phase of said readout clock to provide synchronized readout signals; buffer memory means for temporarily accumulating said synchronized readout signals; decoder means for decoding signals received from the buffer memory; and means for sequencing data signals from the buffer memory in synchronization with the second phase of the readout clock means and through the decoder into a calculator input at a rate commensurate with the input entry rate of the calculator.
Claim 3
Dependent Claim
33 words
A measurement transducer/calculator interface as set forth in claim 1, wherein is provided means for doubling the frequency of the shaped pulse signals for input into the scaling means for improving scaling resolution.
Claim 4
Dependent Claim
31 words
A meausrement transducer/calculator interface as set forth in claim 1, wherein is provided direction control means for determining addition or subtraction of signals sequenced from the buffer memory into the calculator.
Claim 5
Dependent Claim
33 words
A measurement transducer/calculator interface as set forth in claim 1, wherein is also provided coupled to the output of said scaling means an audibilizer for providing audible signals corresponding to said scaled signals.
Claim 6
Dependent Claim
225 words
A measurement transducer/calculator interface for processing output signals from one or more measurement transducers for input to an electronic calculator where at least one of the measurement transducers generates data signals at a rate faster than the highest reliable keyboard entry rate of the calculator comprising: means for receiving and shaping data signals from a measurement transducer at the rate generated by the measurement transducer; means for doubling the frequency of said received data signals; means for adjusting said data signals to a selected scale factor setting; two-phase readout clock means for generating a clock signal having first and second phases; means for synchronizing the processed data signals with the first phase of the clock signal to provide synchronized readout signals; buffer memory means for temporarily accumulating said synchronized readout signals; decoder means for decoding signals received from the buffer memory; means for sampling and sequencing data signals from the buffer memory through the decoder into a calculator input at a rate commensurate with the input speed of the calculator, said sampling of the buffer memory synchronized with the second phase of said clock signal whereby data signal input to the buffer memory never occurs at a time when the buffer is being sampled and unloaded; and direction control means for determining addition or subtraction of signals sequenced from the buffer memory into the calculator.
Claim 7
Dependent Claim
225 words
A measurement transducer/calculator interface for processing output signals from one or more measurement transducers for input to an electronic calculator where at least one of the measurement transducers generates data signals at a rate faster than the highest reliable keyboard entry rate of the calculator comprising: means for receiving and shaping data signals from a measurement transducer at the rate generated by the measurement transducer; means for doubling the frequency of said received data signals; means for adjusting said data signals to a selected scale factor setting; two-phase readout clock means for generating a clock signal having first and second phases; means for synchronizing the processed data signals with the first phase of the clock signal to provide synchronized readout signals; buffer memory means for temporarily accumulating said synchronized readout signals; decoder means for decoding signals received from the buffer memory; means for sampling and sequencing data signals from the buffer memory through the decoder into a calculator input at a rate commensurate with the input speed of the calculator, said sampling of the buffer memory synchronized with the second phase of said clock signal whereby data signal input to the buffer memory never occurs at a time when the buffer is being sampled and unloaded; and direction control means for determining addition or subtraction of signals sequenced from the buffer memory into the calculator.
Claim 8
Dependent Claim
25 words
A measurement transducer/calculator interface as set forth in claim 5 wherein is provided an audibilizer for providing audible signals corresponding to the scaled data signals.
Claim 9
Independent Claim
184 words
A method for interfacing output data signals from one or more measurement transducers for input to an electronic calculator comprising: receiving and shaping data signals from a measurement transducer at the rate generated by the measurement transducer; scaling said data signals; generating a two-phase readout clock signal having first and second phases; synchronizing the processed data signals with the first phase of such readout clock signal to provide synchronized readout data signals; temporarily accumulating the synchronized readout data signals in a buffer memory; sampling and sequencing the data signals from the buffer memOry into a calculator input at a rate commensurate with the input entry rate of the calculator; synchronizing said sampling and sequencing of the data signals from the buffer memory with the second phase of the readout clock signal whereby data signal input to the buffer memory never occurs at a time when the buffer is being unloaded; decoding data signal sequenced from the buffer memory prior to entry at the calculator input; and determining the direction of transition controlled by data signals entered at the calculator input for addition or subtraction.
Claim 10
Independent Claim
184 words
A method for interfacing output data signals from one or more measurement transducers for input to an electronic calculator comprising: receiving and shaping data signals from a measurement transducer at the rate generated by the measurement transducer; scaling said data signals; generating a two-phase readout clock signal having first and second phases; synchronizing the processed data signals with the first phase of such readout clock signal to provide synchronized readout data signals; temporarily accumulating the synchronized readout data signals in a buffer memory; sampling and sequencing the data signals from the buffer memOry into a calculator input at a rate commensurate with the input entry rate of the calculator; synchronizing said sampling and sequencing of the data signals from the buffer memory with the second phase of the readout clock signal whereby data signal input to the buffer memory never occurs at a time when the buffer is being unloaded; decoding data signal sequenced from the buffer memory prior to entry at the calculator input; and determining the direction of transition controlled by data signals entered at the calculator input for addition or subtraction.
Claim 11
Dependent Claim
23 words
A method as set forth in claim 7 wherein is provided the step of doubling the frequency of data signals prior to scaling.
References Cited (Backward Citations)
US3132262A
Cited
US3246128A
Cited
US3393299A
Cited
US3509329A
Cited
US3623010A
Cited
US3582906A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-03 | 1977-06-04 | 1977-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-03 | 1981-06-04 | 1981-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-03 | 1985-06-04 | 1985-12-04 | $7700.00 | Window Closed / Lapsed |