US3777121A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic counter
Assignee: Rothmans Benson and Hedges Inc
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Filing: 1972-11-06
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Granted: 1973-12-04
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Expires: 1992-11-06
Abstract
Abstract An electronic counter is provided with a built-in timer and is fabricated primarily of logic gates having a NAND function. Two of these gates are cross-connected in such a way that one of them is latched so as not to change its output while a timing cycle is taking place. The presence of the timer enables the counter to give a direct readout in RPM, for example.
Inventors
- 👤 P Jamieson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:34
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/02; G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; G01R; G01R23/00; G01R23/02; G01R23/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
566 words
An electronic counter comprising first, second, third, fourth, fifth and sixth logic gates each having a NAND function, each of said logic gates having first and second input terminals and an output terminal; a timer having an output terminal at which a 1 pulse signal is developed after a predetermined timing interval following commencement of a timing cycle by said timer and at which a 0 signal is developed at all other times, said 0 and 1 signals being signals at two different voltage levels; a readout-counter device having an input terminal and constructed and arranged to count and display the number of pulses applied to said input terminal thereof; means connecting said output terminal of said first logic gate and said input terminals of said second logic gate for applying 0 and 1 signals developed at said output terminal of said first logic gate to said input terminals of said second logic gate; means connecting said output terminal of said second logic gate and said first input terminal of said third logic gate for applying 0 and 1 signals developed at said output terminal of said second logic gate to said first input terminal of said third logic gate; means connecting said output terminal of said third logic gate and said first input terminal of said fourth logic gate for applying 0 and 1 signals developed at said output terminal of said third logic gate to said input terminal of said fourth logic gate; means connecting said output terminal of said fourth logic gate and said second input terminal of said third logic gate for applying 0 and 1 signals developed at said output terminal of said fourth logic gate to said second input terminal of said third logic gate; means connecting said output terminal of said timer and said input terminals of said fifth logic gate for applying said 0 and 1 signals developed at said output terminal of said timer to said input terminals of said fifth logic gate; means connecting said output terminal of said fifth logic gate and said second input terminal of said fourth logic gate for applying 0 and 1 signals developed at said output terminal of said fifth logic gate to said second input terminal of said fourth logic gate; means connecting said output terminal of said third logic gate and said first input terminal of said sixth logic gate for applying 0 and 1 signals developed at said output terminal of said third logic gate to said first input terminal of said sixth logic gate; means connecting said output terminal of said sixth logic gate and said input terminal of said readout-counter device for supplying pulses to be counted to said input terminal of said readoutcounter device; means for applying 0 and 1 signals to said second input terminal of said sixth logic gate to develop pulses to be counted at said output terminal of said sixth logic gate; means for applying 0 and 1 signals to said first input terminal of said first logic gate; means for applying at lEast 1 signals to said second input terminal of said first logic gate; and means responsive to a 0 signal at said output terminal of said fourth logic gate for commencing a timing cycle of said timer and for terminating said timing cycle responsive to a 1 signal at said output terminal of said fourth logic gate.
Claim 2
Dependent Claim
566 words
An electronic counter comprising first, second, third, fourth, fifth and sixth logic gates each having a NAND function, each of said logic gates having first and second input terminals and an output terminal; a timer having an output terminal at which a 1 pulse signal is developed after a predetermined timing interval following commencement of a timing cycle by said timer and at which a 0 signal is developed at all other times, said 0 and 1 signals being signals at two different voltage levels; a readout-counter device having an input terminal and constructed and arranged to count and display the number of pulses applied to said input terminal thereof; means connecting said output terminal of said first logic gate and said input terminals of said second logic gate for applying 0 and 1 signals developed at said output terminal of said first logic gate to said input terminals of said second logic gate; means connecting said output terminal of said second logic gate and said first input terminal of said third logic gate for applying 0 and 1 signals developed at said output terminal of said second logic gate to said first input terminal of said third logic gate; means connecting said output terminal of said third logic gate and said first input terminal of said fourth logic gate for applying 0 and 1 signals developed at said output terminal of said third logic gate to said input terminal of said fourth logic gate; means connecting said output terminal of said fourth logic gate and said second input terminal of said third logic gate for applying 0 and 1 signals developed at said output terminal of said fourth logic gate to said second input terminal of said third logic gate; means connecting said output terminal of said timer and said input terminals of said fifth logic gate for applying said 0 and 1 signals developed at said output terminal of said timer to said input terminals of said fifth logic gate; means connecting said output terminal of said fifth logic gate and said second input terminal of said fourth logic gate for applying 0 and 1 signals developed at said output terminal of said fifth logic gate to said second input terminal of said fourth logic gate; means connecting said output terminal of said third logic gate and said first input terminal of said sixth logic gate for applying 0 and 1 signals developed at said output terminal of said third logic gate to said first input terminal of said sixth logic gate; means connecting said output terminal of said sixth logic gate and said input terminal of said readout-counter device for supplying pulses to be counted to said input terminal of said readoutcounter device; means for applying 0 and 1 signals to said second input terminal of said sixth logic gate to develop pulses to be counted at said output terminal of said sixth logic gate; means for applying 0 and 1 signals to said first input terminal of said first logic gate; means for applying at lEast 1 signals to said second input terminal of said first logic gate; and means responsive to a 0 signal at said output terminal of said fourth logic gate for commencing a timing cycle of said timer and for terminating said timing cycle responsive to a 1 signal at said output terminal of said fourth logic gate.
Claim 3
Dependent Claim
16 words
The invention according to claim 1 wherein said sixth logic gate is a Schmitt trigger circuit.
Claim 4
Dependent Claim
153 words
The invention according to claim 1 wherein said means connecting said input terminal of said sixth logic gate and said input terminal of said readout-counter device comprises a seventh logic gate having a NAND function and having first and second input terminals and an output terminal, means connecting said output terminal of said sixth logic gate and said first input terminal of said seventh logic gate for applying 0 and 1 signals developed at said output terminal of said sixth logic gate to said first input terminal of said seventh logic gate, and means connecting said output terminal of said seventh logic gate, and said input terminal of said readout-counter device for applying pulses to be counted developed at said output terminal of said seventh logic gate to said input terminal of said readout-counter device; and means for applying 0 and 1 signals to said second input terminal of said seventh logic gate.
Claim 5
Dependent Claim
16 words
The invention according to claim 3 wherein said seventh logic gate is a Schmitt trigger circuit.
Claim 6
Dependent Claim
31 words
The invention according to claim 1 wherein said means connecting said output terminal of said third logic gate and said first input terminal of said sixth logic gate includes a switch.
Claim 7
Dependent Claim
26 words
The invention according to claim 1 wherein said means for applying 0 signals to said first input terminal of said first logic gate includes a switch.
Claim 8
Dependent Claim
135 words
The invention according to claim 1 including a relay having a coil and contacts, said means responsive to 0 and 1 signals at said output terminal of said fourth logic gate comprising said coil and contacts and a circuit including said coil through which current can flow, said circuit including a device that is conductive and renders said circuit conductive in response to one of said signals being developed at said output terminal of said fourth logic gate and that is non-conductive and renders said circuit non-conductive in response to the other of said signals being developed at said output terminal of said fourth logic gate, said timer including a timing capacitor that charges during said timing cycle, said relay contacts being connected in parallel with said timing capacitor and preventing charging thereof when closed.
Claim 9
Dependent Claim
12 words
The invention according to claim 7 wherein said device is a transistor.
Claim 10
Dependent Claim
13 words
The invention according to claim 1 wherein said logic gates are NAND gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-03 | 1977-06-04 | 1977-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-03 | 1981-06-04 | 1981-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-03 | 1985-06-04 | 1985-12-04 | $7700.00 | Window Closed / Lapsed |