An error correcting encoder

Claim 2

An error correcting encoder comprising: an encoder input for input analog signals having an information containing parameter to be encoded; first means to generate an initial code signal representative of said parameter; second means coupled to said first means to produce an analog replica of said initial code signal; third means coupled to said encoder input and said second means to produce an error signal when said analog replica and said input analog signals differ; and fourth means coupled to said first means and said third means responsive to said error signal to correct said initial code signal and produce an error corrected output code signal.

Claim 3

An encoder according to claim 1, wherein said first means includes a code generator coupled to said encoder input to produce said initial code signal, and a storage means coupled to said code generator to store said initial code signal.

Claim 4

An encoder according to claim 1, wherein said second means includes a decoder coupled to said first means to produce said analog replica.

Claim 5

An encoder according to claim 1, wherein said third means includes an analog comparison circuit coupled to said encoder input and the output of said second means to produce sAid error signal.

Claim 6

An encoder according to claim 1, wherein said fourth means includes an error correcting circuit coupled to said first means and said third means responsive to said error signal to correct said initial code signal and to produce said error corrected output code signal.

Claim 7

An encoder according to claim 1, wherein said first means includes a code generator coupled to said encoder input to produce said initial code signal, and a storage means coupled to said code generator to store said initial code signal; said second means includes a decoder coupled to said storage means to produce said analog replica; said third means includes an analog comparison circuit coupled to said encoder input and the output of said decoder to produce said error signal; and said fourth means includes an error correcting circuit coupled to said storage means and said comparison circuit responsive to said error signal to correct said initial code signal stored in said storage means and to produce said error corrected output code signal.

Claim 8

An encoder according to claim 1, wherein said first means, said second means and said third means cooperate to produce a high order reference signal, to store said high order reference signal when said error signal has a first given condition, to reject said high order reference signal when said error signal has a second given condition different than said first given condition, to produce a lower order reference signal, to store said lower order reference signal when said error signal has said first given condition, to reject said lower order reference signal when said error signal has said second given condition, to successively produce lower order reference signals, to successively store each of said lower order reference signals when said error signal has said first given condition, and to successively reject each of said lower order reference signals when said error signal has said second given condition; and said initial code signal includes those reference signals that are stored.

Claim 9

An encoder according to claim 7, wherein said fourth means corrects said stored reference signals by appropriately adding and subtracting successive ones of lower order reference signals to and from preceding reference signals; and said error corrected output code signals are produced from said corrected stored reference signals.

Claim 10

An encoder according to claim 8, wherein said fourth means generates a lowest order reference signal and performs a first final correction to said stored reference signals by adding said lowest order reference signal to previously stored reference signals or rejecting said lowest order reference signal in response to certain predetermined conditions of said error signal, and performs a second final correction to said stored reference signals by subtracting said lowest order reference signal from previously stored reference signals or rejecting said lowest order reference signal in response to other predetermined conditions of said error signal.

Claim 11

An encoder according to claim 9, wherein said fourth means performs said first final correction if at the penultimate correction said initial code signal has a value which is below the level of the highest order reference signal and said second final correction if at the penultimate correction said initial code signal has a value which is above the level of the highest order reference signal.

Claim 12

An encoder according to claim 1, wherein said first means and said fourth means includes a reference signal generating circuit, a storage circuit coupled in tandem to said generating circuit, an error correcting circuit coupled in tandem to said storage circuit, an output circuit coupled in tandem to said correcting circuit, and a timing circuit connected to said generating circuit, said storage circuit, said correcting circuit and said output circuit to time the operation thereof; said second means includes a decoder coupled to said storage circuit to produce said analog replica; and said third means includes a comparator circuit having one input coupled to said encoder input, another input coupled to the output of said decoder and an output to couple said error signal to said timing circuit; said generating circuit producing reference signals for representing the value of said parameter during a predetermined time interval; said storage circuit storing required ones of said reference signals as said initial code signal and applying said stored ones of said reference signals to said correcting circuit; said timing circuit responding to said error signal to produce control signals; said correcting circuit responding to said control signals to alter said initial code signal so that said stored reference signals represent more accurately the value of said parameter; and said output circuit produces said error corrected output code signal from said corrected stored initial code signal.

Claim 13

An encoder according to claim 11, wherein said generating circuit produces binary code signals having binary digits representing successively decreasing values of said parameter, each of said digits being present at a different output of said generating circuit; and said storage circuit only stores the highest value binary signal in response to a first control signal produced by said timing circuit in response to said error signal indicating that said parameter of said input analog signal is greater than said parameter of said analog replica and to a second control signal produced by said timing circuit in response to said error signal indicating that said parameter of said input analog signal is less than said parameter of said analog replica.

Claim 14

An encoder according to claim 12, wherein said correcting circuit includes a counting circuit.

Claim 15

An encoder according to claim 13, wherein during a first part of an encoding cycle said generating circuit generates a given number of said digits for the remainder of said encoding cycle in response to said first control signal, and during a second part of said encoding cycle said counting circuit is loaded with said given number of said digits and after loading adds each of a plurality of binary unit steps in response to one of said first and second control signals and subtracts each of a plurality of binary unit steps in response to the other of said first and second control signals.

Claim 16

An encoder according to claim 14, wherein said output circuit produces said error corrected output code signal as a succession of digits in series, and said encoding cycle is controlled by said timing circuit to have a duration substantially equal to the duration of said error corrected output code signal produced by said output circuit.