Abstract A drift-compensated, electronic sample hold circuit for delivering a control signal to a valve or other final control element in a process control system in order to hold its position. The sample hold circuit is constituted by an amplifier and a memory capacitor. The drift compensation means associated with the sample hold circuit comprises a converter that converts the output of the sample hold circuit to a pulse train signal whose frequency is a function of the output voltage of the sample hold circuit, a clock pulse generator that yields a clock pulse signal having a predetermined frequency, an AND gate responsive to the pulse train signal and the clock pulse signal to produce an output signal only when the signals applied thereto overlap, and a sample drive circuit responsive to the output signal from the AND gate to produce a compensation signal which is fed to the input of the sample hold circuit.
A drift-compensated sample hold circuit comprising: a. a sample hold circuit constituted by an amplifier and a memory capacitor, b. a converter coupled to the output of said sample hold circuit to convert the output thereof to a pulse train signal having a frequency which is a function of the output voltage of said sample hold circuit, c. a clock pulse generator yielding a clock pulse signal having a predetermined frequency, d. an AND-gate coupled to said converter and said generator to receive said pulse train signal and said clock pulse signal and yielding an output signal only when said signals overlap, and e. a sample drive circuit coupled to the input of said sample hold circuit for delivering a compensation signal thereto in response to the output signal of said gate.
Claim 2
Dependent Claim
132 words
A drift-compensated sample hold circuit comprising: a. a sample hold circuit constituted by an amplifier and a memory capacitor, b. a converter coupled to the output of said sample hold circuit to convert the output thereof to a pulse train signal having a frequency which is a function of the output voltage of said sample hold circuit, c. a clock pulse generator yielding a clock pulse signal having a predetermined frequency, d. an AND-gate coupled to said converter and said generator to receive said pulse train signal and said clock pulse signal and yielding an output signal only when said signals overlap, and e. a sample drive circuit coupled to the input of said sample hold circuit for delivering a compensation signal thereto in response to the output signal of said gate.